Display device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11575100-B2
Application number	US-202017082459-A
Country	US
Kind code	B2
Filing date	Oct 28, 2020
Priority date	Sep 2, 2016
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.

First claim

What is claimed is:

1. A display device comprising:
a base substrate;
a first transistor above the base substrate and comprising a first channel area to a first insulation layer and a first Rate above the first insulation layer and below a second insulation layer;
a second transistor above the base substrate and comprising a second gate above the first insulation layer and below the second insulation layer, a second channel area above the second insulation layer and a third gate above the first and the second insulation layers and electrically connected to the second gate;
a third transistor above the base substrate and comprising a third channel area below the first insulation layer and a fourth gate above the first insulation layer and below the second insulation layer; and
a light emitting diode above the second insulation layer,
wherein the first transistor is electrically connected to the second transistor, and
the first transistor is electrically coupled to the third transistor.

2. The display device of claim 1 , wherein the first channel area comprises polysilicon semiconductor and the second channel area comprises an oxide semiconductor.

3. The display device of claim 2 , wherein the third channel area comprises polysilicon semiconductor.

4. The display device of claim 2 , wherein the oxide semiconductor comprises vertical crystals.

5. The display device of claim 1 , further comprise at least one third insulation layer above the second insulation layer.

6. The display device of claim 1 , further comprising a power line to which a first voltage is applied, and
wherein the first transistor is electrically disposed between the power line and the third transistor.

7. The display device of claim 6 , wherein the third transistor is electrically disposed between the first transistor and the light emitting diode.

8. The display device of claim 1 , further comprising a scan line to which a scan signal is applied, and
wherein the second transistor is turned on by the scan signal.

9. The display device of claim 8 , further comprising a light emitting line to which a control signal is applied, and
wherein the third transistor is turned on by the control signal.

10. The display device of claim 1 , wherein the second transistor is electrically coupled to a scan line, and
the third transistor is electrically coupled to a light emitting line different from the scan line.

11. The display device of claim 1 , further comprising a power line to which a first voltage is applied, and
wherein the third transistor is electrically disposed between the power line and the first transistor.

12. A display device comprising:
a base substrate;
a first transistor above the base substrate and comprising a first channel area below a first insulation layer and a first gate above the first insulation layer and below a second insulation layer;
a second transistor above the base substrate and comprising a second gate above the first insulation layer and below the second insulation layer, a second channel area above the second insulation layer and a third gate above the first and the second insulation layers;
a third transistor above the base substrate and comprising a third channel area below the first insulation layer, and a fourth gate above the first insulation layer and below the second insulation layer; and
a light emitting diode above the second insulation layer,
wherein the first channel area comprises polysilicon semiconductor,
the second channel area comprises an oxide semiconductor,
the first channel area is disposed on a layer different from the second channel area, and
the first transistor is electrically coupled to at least one of the second transistor and the third transistor.

13. The display device of claim 12 , wherein the third channel area comprises polysilicon semiconductor.

14. The display device of claim 12 , wherein the third channel area is disposed on a same layer as the first channel area.

15. The display device of claim 12 , wherein the oxide semiconductor comprises vertical crystals.

16. The display device of claim 12 , further comprise at least one third insulation layer above the second insulation layer.

17. The display device of claim 12 , further comprising a power line to which a first voltage is applied, and
wherein the first transistor is electrically disposed between the power line and the third transistor.

18. The display device of claim 17 , wherein the third transistor is electrically disposed between the first transistor and the light emitting diode.

19. The display device of claim 12 , further comprising a scan line to which a scan signal is applied, and
wherein the second transistor is turned on by the scan signal.

20. The display device of claim 19 , further comprising a light emitting line to which a control signal is applied, and
wherein the third transistor is turned on by the control signal.

21. The display device of claim 12 , wherein the second transistor is electrically coupled to a scan line, and
the third transistor is electrically coupled to a light emitting line different from the scan line.

22. The display device of claim 12 , further comprising a power line to which a first voltage is applied, and
wherein the third transistor is electrically disposed between the power line and the first transistor.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Jaybum
• Kim Eoksu
• SON Kyoungseok
• LIM Junhyung
• Lim Jihun

Classifications

• H10K59/12

  Active-matrix OLED [AMOLED] displays · CPC title

• H10K50/805

  Electrodes · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title