Thin-film transistor array substrate, display device including the same, and method of manufacturing the thin-film transistor array substrate

Patent metadata

Field	Value
Publication number	US-9245908-B2
Application number	US-201414243694-A
Country	US
Kind code	B2
Filing date	Apr 2, 2014
Priority date	Aug 16, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A method of manufacturing a thin film transistor (TFT) array substrate is disclosed. In one aspect, the method includes forming an active layer on a substrate, forming a first insulating layer on the substrate to cover the active layer, and forming a first gate electrode on the first insulating layer in an area corresponding to the active layer, doping the active layer with ion impurities, forming a second insulating layer on the first insulating layer to cover the first gate electrode, performing an annealing process on the active layer, forming a lower electrode of a capacitor on the second insulating layer, forming a third insulating layer on the second insulating layer to cover the lower electrode, wherein the third insulating layer has a dielectric constant that is greater than those of the first and second insulating layers, and forming an upper electrode of the capacitor on the third insulating layer.

First claim

What is claimed is:

1. A method of manufacturing a thin film transistor (TFT) array substrate, comprising:
forming an active layer over a substrate;
forming a first insulating layer over the substrate to cover the active layer;
forming a first gate electrode over the first insulating layer, wherein the first gate electrode is formed substantially directly above at least a portion of the active layer;
doping the active layer with ion impurities;
forming a second insulating layer over the first insulating layer to cover the first gate electrode, wherein the second insulating layer includes top and bottom surfaces opposing each other, and wherein the bottom surface faces the substrate;
performing an annealing process on the active layer;
forming a lower electrode of a capacitor over the second insulating layer, wherein the top surface of the second insulating layer contacts the lower electrode;
forming a third insulating layer over the second insulating layer to cover the lower electrode, wherein the third insulating layer has a dielectric constant greater than those of the first and second insulating layers; and
forming an upper electrode of the capacitor over the third insulating layer.

2. The method of claim 1 , wherein the forming of the active layer comprises forming a first active layer and a second active layer.

3. The method of claim 2 , wherein the forming of the lower electrode comprises substantially simultaneously forming i) a second gate electrode over the third insulating layer to be substantially directly above at least a portion of the second active layer and ii) the lower electrode of the capacitor.

4. The method of claim 2 , wherein the forming of the first gate electrode comprises forming the first gate electrode and a third gate electrode to be substantially directly above at least portions of the first and second active layers, respectively, and wherein the doping of the active layer comprises doping the first active layer and the second active layer with ion impurities.

5. The method of claim 4 , wherein the third gate electrode comprises a floating gate electrode.

6. The method of claim 4 , wherein the forming of the first and third gate electrodes
comprises using a halftone mask having a transmission region which is formed substantially directly above at least a portion of the first gate electrode and a semi-transmission region which is formed substantially directly above at least a portion of the third gate electrode.

7. The method of claim 6 , wherein the forming of the first and third gate electrodes comprises:
forming a gate electrode layer over the first insulating layer;
selectively etching the gate electrode layer via the halftone mask to form the first and third gate electrodes;
doping the first and second active layers with ion impurities using the first and third gate electrodes as masks; and
etching the third gate electrode from the substrate.

8. The method of claim 1 , wherein the forming of the upper electrode of the capacitor comprises substantially simultaneously forming over the third insulating layer i) a source electrode and a drain electrode to be substantially directly above at least a portion of the active layer and ii) the upper electrode of the capacitor.

9. The method of claim 1 , wherein the third insulating layer has a dielectric constant ranging from about 15 to about 40.

10. A thin film transistor (TFT) array substrate, comprising:
an active layer formed over the substrate;
a first insulating layer formed over the substrate to cover the active layer;
a first gate electrode formed over the first insulating layer, wherein the first gate electrode is formed substantially directly above at least a portion of the active layer;
a second insulating layer formed over the first insulating layer to cover the first gate electrode, wherein the second insulating layer includes top and bottom surfaces opposing each other, and wherein the bottom surface faces the substrate;
a lower electrode of a capacitor formed over the second insulating layer, wherein the top surface of the second insulating layer contacts the lower electrode;
a third insulating layer formed over the second insulating layer to cover the lower electrode, wherein the third insulating layer has a dielectric constant greater than those of the first and second insulating layers; and
an upper electrode of the capacitor formed over the third insulating layer.

11. The TFT array substrate of claim 10 , wherein the active layer comprises a first active layer and a second active layer.

12. The TFT array substrate of claim 11 , further comprising a second gate electrode formed over the second insulating layer, wherein the second gate electrode is formed substantially directly above at least a portion of the second active layer, and wherein the second gate electrode is formed in the same layer as that of the lower electrode.

13. The TFT array substrate of claim 11 , further comprising a third gate electrode formed substantially directly above at least a portion of the second active layer, wherein the third gate electrode is a floating gate electrode.

14. The TFT array substrate of claim 10 , wherein the active layer comprises i) a source region and a drain region doped with ion impurities, and ii) a channel region connecting the source and drain regions to each other, wherein the TFT array substrate further comprises a source electrode and a drain electrode that are respectively electrically connected to the source and drain regions and formed over the third insulating layer to be substantially directly above at least portions of the source and drain regions, respectively, and wherein the source and drain electrodes are formed in the same layer as that of the upper electrode.

15. A display device comprising:
a substrate; and
a plurality of pixels, each including a pixel circuit comprising:
an active layer formed over the substrate;
a first insulating layer formed over the substrate to cover the active layer;
a first gate electrode formed over the first insulating layer in an area corresponding to the active layer;
a second insulating layer formed over the first insulating layer to cover the first gate electrode, wherein the second insulating layer includes top and bottom surfaces opposing each other, and wherein the bottom surface faces the substrate;
a lower electrode of a capacitor formed over the second insulating layer, wherein the top surface of the second insulating layer contacts the lower electrode;
a third insulating layer formed over the second insulating layer to cover the lower electrode, wherein the third insulating layer has a dielectric constant that is greater than those of the first and second insulating layers; and
an upper electrode of the capacitor formed over the third insulating layer.

16. The display device of claim 15 , wherein the active layer comprises a first active layer and a second active layer.

17. The display device of claim 16 , further comprising a second gate electrode formed over the second insulating layer, wherein the second gate electrode is formed substantially directly above at least a portion of the second active layer, wherein the second gate electrode is formed in the same layer as that of the lower electrode.

18. The display device of claim 16 , further comprising a third gate electrode formed between the second gate electrode and the second active layer, wherein the first gate electrode is formed substantially directly above at least a portion of the first active layer, and wherein

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Jeong-Ho
• Sim Su-Yeon
• Yoon Ju-Won
• Lee Seung-Min
• Lee Wang-Woo
• Lee Il-Jeong
• Lee Jung-Kyu
• Im Choong-Youl

Classifications

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/431 Primary

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L27/1288

  Electricity · mapped topic