Feeder design with high current capability

Patent metadata

Field	Value
Publication number	US-11575007-B2
Application number	US-202117448790-A
Country	US
Kind code	B2
Filing date	Sep 24, 2021
Priority date	Sep 15, 2017
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A feeder design is manufactured as a structure in a SIC semiconductor material comprising at least two p-type grids in an n-type SiC material (3), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3) wherein the at least two p-type grids (4, 5) are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material (3) between the first and a second regions without any grids.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
an n-type substrate;
a drift layer disposed on the n-type substrate;
an n-type SiC material disposed on the drift layer;
at least two p-type grids disposed in a first horizontal level, parallel with the n-type substrate, in the n-type SiC material; and
a PiN diode structure comprising:
at least one epitaxially grown p-type region disposed in a second horizontal level, parallel with the n-type substrate, on the n-type SiC material disposed on the drift layer, the at least one epitaxially grown p-type region defined within a boundary line of the second level;
an n-type epitaxially grown layer of SiC disposed in contact with the at least two p-type grids and the n-type SiC material and disposed in contact with the at least one epitaxially grown p-type region; and
an Ohmic contact disposed in contact with the at least one epitaxially grown p-type region,

wherein the at least two p-type grids are disposed within a maximum value of a surrounding distance in a horizontal direction from the boundary line, and wherein the at least two p-type grids have a top surface disposed at a vertical separation in a vertical direction from a bottom surface of the at least one epitaxially grown p-type region, the vertical separation being in a range between contact and the maximum value.

2. The semiconductor device of claim 1 , wherein:
the at least one epitaxially grown p-type region is disposed in contact with at least one of the at least two p-type grids; or
the at east one epitaxially grown p-type region is not disposed in contact with the at least two p-type grids; or
the at least one epitaxially grown p-type region is applied directly on the at least two p-type grids in the n-type SiC material.

3. The semiconductor device of claim 1 , wherein:
the at least two p-type grids each comprises a plurality of ion implanted grids; or
the at least two p-type grids are manufactured by ion implantation.

4. The semiconductor device of claim 1 , wherein the maximum value is 0.5 μm.

5. The semiconductor device of claim 4 , wherein:
a width of the at least one epitaxially grown p-type region is in the interval 5 μm to 500 μm; or
a thickness of the at least one epitaxially grown p-type region is in the interval 1 μm to 3 μm; or
a thickness of the epitaxially grown n-type layer is at least 0.5 μm thicker than the at least one epitaxially grown p-type region.

6. The semiconductor device of claim 4 , wherein the at least two p-type grids comprise at least three of the at least two p-type grids, and wherein a space between adjacent ones of the at least three p-type grids is in an interval of 1 μm to 5 μm, not taking into account a region in the n-type SiC material between a first region and a second region without any grids as a space.

7. The semiconductor device of claim 1 , wherein:
a doping concentration of the at least one epitaxially grown p-type region varies from closest to the n-type SiC material to closest to the Ohmic contact: or
a doping concentration of the at least one epitaxially grown p-type region is highest closest to the Ohmic contact.

8. The semiconductor device of claim 1 , comprising a connection disposed in a space between the at least one epitaxially grown p-type region and the at least two p-type grids.

9. The semiconductor device of claim 1 , wherein the at least two p-type grids comprise a plurality of the at least two p-type grids, wherein at least a part of the grids has a ledge positioned centered under the grids, the ledge positioned in the vertical direction away from the n-type epitaxially grown layer, the ledge having a smaller lateral dimension than the grids.

10. The semiconductor device of claim 1 , wherein the at least two p-type grids comprise a plurality of the at least two p-type grids; wherein each p-type grid comprises an upper part and a lower part, the upper part being towards the n-type epitaxially grown layer; wherein the upper part is manufactured using epitaxial growth; and wherein the lower part is manufactured using ion implantation.

11. The semiconductor device of claim 1 , wherein the semiconductor device is selected from the group consisting of a MOSFET, a JFET, a JBS diode, and an insulated-gate bipolar transistor (IGBT).

12. The semiconductor device of claim 11 , wherein the semiconductor device is an integration of at least two components.

13. A method for the manufacture of a structure in SiC comprising the steps of:
a) providing a substrate with a drift layer and an n-type SiC material on top;
b) adding a p-type layer by epitaxial growth of SiC;
c) etching away unwanted parts of the added p-type layer to obtain at least one epitaxially grown p-type region, the at least one epitaxially grown p-type region being in a second level and defined within a boundary line of the second level;
d) creating at least two p-type grids in a first level in the n-type SiC material;
e) adding an n-type layer by epitaxial growth of SiC,
wherein the at least two p-type grids are disposed within a maximum surrounding distance in the first level from the boundary line and are disposed at a separation from the at least one epitaxially grown p-type region in the second level, the separation being in a range of 0 to the maximum surrounding distance.

14. The method of claim 13 , wherein step d) is carried out before step b).

15. The method of claim 13 , wherein step d) is carried out by ion implantation.

16. The method of claim 15 , wherein the steps are carried out in the order: a), d), e), b), c) with an additional step of etching a trench in the n-type layer after step e), in a region intended for the at least one epitaxially grown p-type region.

Assignees

• Ii Vi Delaware Inc

Inventors

• Elahipanah Hossein
• Thierry-Jebali Nicolas
• Schöner Adolf
• Reshanov Sergey

Classifications

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D62/106 Primary

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D8/021

  of breakdown diodes · CPC title

• H10D8/20

  Breakdown diodes, e.g. avalanche diodes · CPC title

• H10D8/051

  of Schottky diodes · CPC title