Silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-2016126347-A1
Application number	US-201414895900-A
Country	US
Kind code	A1
Filing date	May 8, 2014
Priority date	Jun 12, 2013
Publication date	May 5, 2016
Grant date	—

Abstract

A trench reaches a first layer of a first conductivity type from a second main surface through a third layer of the first conductivity type and a second layer of a second conductivity type. A contact region extends from the second main surface through the third layer and the second layer to a position deeper than an interface between the first layer and the second layer, and comes in contact with an embedded region. The contact region is higher in impurity concentration than the second layer. The embedded region has a first portion lying between the contact region and a first main surface in a direction of thickness and a second portion extending from the first portion toward the trench.

First claim

1 . A silicon carbide semiconductor device, comprising:
a silicon carbide layer having a direction of thickness and having a first main surface and a second main surface opposed to said first main surface in said direction of thickness, said silicon carbide layer including
a first layer forming said first main surface and having a first conductivity type,
a second layer provided on said first layer as being spaced apart from said first main surface by said first layer and having a second conductivity type, and
a third layer provided on said second layer as being spaced apart from said first layer by said second layer, forming said second main surface, and having said first conductivity type,
said silicon carbide layer being provided with a trench having a sidewall surface reaching said first layer from said second main surface through said third layer and said second layer, said silicon carbide layer further including
a contact region which extends from said second main surface through said third layer and said second layer to a position deeper than an interface between said first and second layers, is distant from said first main surface, has said second conductivity type, and is higher in impurity concentration than said second layer, and
an embedded region which is distant from each of said first main surface, said second main surface, said second layer, said third layer, and said trench, is in contact with said contact region, and has said second conductivity type, said embedded region having a first portion lying between said contact region and said first main surface in said direction of thickness and a second portion extending from said first portion toward said trench;
a gate insulating film provided on said trench; a gate electrode provided on said gate insulating film; a first electrode provided on said first main surface of said silicon carbide layer; and a second electrode provided on said second main surface of said silicon carbide layer and being in contact with each of said third layer and said contact region.

2 . The silicon carbide semiconductor device according to claim 1 , wherein
said first layer includes a first region which forms said first main surface and a second region which is provided between said first region and said second layer and is higher in impurity concentration than said first region, said sidewall surface of said trench reaches said first region through said second region, and said second region is located between said second portion of said embedded region and said second layer in said direction of thickness.

3 . The silicon carbide semiconductor device according to claim 1 , wherein
at least a part of said embedded region is higher in impurity concentration than said second layer.

4 . The silicon carbide semiconductor device according to claim 1 , wherein
said embedded region is distant from said trench by not smaller than 1 μm and not greater than 4 μm.

5 . The silicon carbide semiconductor device according to claim 1 , wherein
said second portion of said embedded region extends by not smaller than 1 μm from said first portion of said embedded region toward said trench.

6 . The silicon carbide semiconductor device according to claim 1 , wherein
on said sidewall surface of said trench, said second layer is provided with a surface including a first surface having a plane orientation {0-33-8}.

7 . The silicon carbide semiconductor device according to claim 6 , wherein
said surface microscopically includes said first surface and said surface microscopically further includes a second surface having a plane orientation {0-11-1}.

8 . The silicon carbide semiconductor device according to claim 7 , wherein
said first and second surfaces of said surface form a combined surface having a plane orientation {0-11-2}.

9 . The silicon carbide semiconductor device according to claim 8 , wherein said surface macroscopically has an off angle of 62°±10° with respect to a {000-1} plane.

Assignees

• Sumitomo Electric Industries

Inventors

• Wada Keiji
• Masuda Takeyoshi

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10D64/01366

  the semiconductor being silicon carbide · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/8325

  Silicon carbide · CPC title