Aluminum-based gallium nitride integrated circuits

Patent metadata

Field	Value
Publication number	US-11569182-B2
Application number	US-202017061075-A
Country	US
Kind code	B2
Filing date	Oct 1, 2020
Priority date	Oct 22, 2019
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

First claim

The claimed invention is:

1. A device having an aluminum (Al) based gallium nitride (GaN) monolithic microwave integrated circuit comprises:
a substrate having:
a barrier layer disposed on the substrate, the barrier region including an AlGaN material and including a drain region, a source region, and a gate region; and
a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a GaN material;

a gate electrical contact disposed on the gate region of the barrier layer, the gate electrical contact including a first metallic layer that includes Al and a second metallic layer that includes a first conductive material;
a source electrical contact disposed on the source region of the barrier layer, the source electrical contact including a third metallic layer that includes Al and a fourth metallic layer that includes a second conductive material that is different from the first conductive material; and
a drain electrical contact disposed on the drain region of the barrier layer, the drain electrical contact including a fifth metallic layer that includes Al and a sixth metallic layer that includes the second conductive material.

2. The device of claim 1 , comprising a capacitor including a first plate, a second plate, and a dielectric material disposed between the first plate and the second plate, wherein:
at least a portion of the first plate is disposed on at least one of the channel layer or the barrier layer;
the second plate is disposed on the dielectric material; and
the first plate and the second plate include an Al-based metal.

3. The device of claim 2 , wherein:
the dielectric material is part of a dielectric material layer that is disposed over at least a portion of the barrier layer, at least a portion of the channel layer, and electrical features disposed on at least one of the barrier layer or the channel layer;
the Al-based metal includes at least 95% Al by weight; and
the dielectric material layer includes silicon dioxide (SiO 2 ) or disilicon trinitride (Si 2 N 3 ).

4. The device of claim 3 , comprising:
a connector coupled to the source electrical contact, the connector including a first portion that passes through the dielectric material layer and a second portion that is disposed on the dielectric material layer, the connector including the Al-based metal.

5. The device of claim 1 , comprising:
a via that passes through the substrate and at least one of the channel layer or the barrier layer, the via being filed at least partially with an Al-based metal and the via is coupled with an electrical feature disposed on at least one of the barrier layer or the channel layer.

6. The device of claim 1 , wherein the first conductive material includes titanium nitride (TiN) and the second conductive material includes titanium (Ti).

7. The device of claim 1 , wherein:
at least a portion of the gate electrical contact has a length from about 100 nm to about 300 the substrate includes silicon carbide (SiC);
a thickness of the substrate is no greater than about 200 micrometers; and
the device includes an additional gate electrical contact disposed on an additional gate region of the barrier layer, the additional gate electrical contact including the first metallic material and at least a portion of a length of the additional gate electrical contact is from about 500 nm to about 1000 nm.

8. A device having an aluminum (Al) based gallium nitride (GaN) monolithic microwave integrated circuit comprises:
a substrate having:
a barrier layer disposed on the substrate, the barrier region including an AlGaN material and including a drain region, a source region, and a gate region; and
a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a GaN material;
a plurality of dielectric layers disposed over the channel layer and the barrier layer;
a first portion of an interconnect device disposed within a first dielectric layer of the plurality of dielectric layers, the first portion of the interconnect device including an Al-based metal; and
a second portion of an interconnect device coupled to the first portion of the interconnect device and disposed within a second dielectric layer of the plurality of dielectric layers, the second portion of the interconnect device including the Al-based metal.

9. The device of claim 8 , comprising:
a gate electrical contact disposed on the gate region of the barrier layer, the gate electrical contact including a first metallic material that includes Al;
a source electrical contact disposed on the source region of the barrier layer, the source electrical contact including a second metallic material that includes Al; and
a drain electrical contact disposed on the drain region of the barrier layer, the drain electrical contact including the second metallic material that includes Al.

10. The device of claim 8 , wherein the interconnect device is coupled to the source electrical contact by a connector disposed in a third dielectric layer of the plurality of dielectric layers.

11. The device of claim 8 , comprising an impedance device disposed on at least one of the channel layer or the barrier layer, and wherein the interconnect device is coupled to the impedance device by a connector disposed in a third dielectric layer of the plurality of dielectric layers.

12. The device of claim 8 , wherein a thickness of the first portion of the interconnect device together with the second portion of the interconnect device is at least 3.5 micrometers.

13. The device of claim 8 , comprising:
a first portion of an inductor device disposed within a dielectric layer of the plurality of dielectric layers, the first portion of the inductor device including the Al-based metal; and
a second portion of the inductor device coupled to the first portion of the inductor device and disposed within an additional dielectric layer of the plurality of dielectric layers, the second portion of the inductor device including the Al-based metal.

14. The device of claim 8 , wherein a first part of the first portion of the interconnect device has a first length and a second part of the first portion of the interconnect device has a second length that is less than the first length, the second part of the first portion of the interconnect device being adjacent to the second portion of the interconnect device.

15. The device of claim 8 , comprising a via that passes through the substrate and at least one of the channel layer or the barrier layer, the via being filed at least partially with an Al-based metal and the via is coupled with an electrical feature disposed on at least one of the barrier layer or the channel layer.

Assignees

• Analog Devices Inc

Inventors

• Piedra Daniel
• Fiorenza James G
• Srivastava Puneet
• Proudman Andrew
• Flanders Kenneth
• Murphy Denis Michael
• Green Leslie P
• Stubler Peter R

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H01L2223/6683

  Electricity · mapped topic

• H01L2223/6616

  Electricity · mapped topic

• H01L29/7786

  Electricity · mapped topic