Method of manufacturing nitride semiconductor device

Patent metadata

Field	Value
Publication number	US-9691875-B2
Application number	US-201514747823-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Nov 17, 2014
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A method of manufacturing a nitride semiconductor device includes: forming a transistor having a gate electrode Schottky-joined to a nitride semiconductor layer; performing high-temperature annealing at a temperature of 200 to 360° C. for 8 to 240 hours on the transistor; and after the high-temperature annealing, performing RF burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° C.

First claim

What is claimed is:

1. A method of manufacturing a wafer comprising a plurality of nitride semiconductor devices comprising:
forming a transistor having a gate electrode Schottky-joined to a nitride semiconductor layer;
performing high-temperature annealing at a temperature of 200 to 360° C. for 8 to 240 hours on the transistor; and
after the high-temperature annealing, performing RF burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° C.,
wherein the RF burn-in reduces a leak current of the Schottky-joined gate electrode, which is present after the high-temperature anneal prior to the RF burn-in.

2. The method of manufacturing the wafer comprising a plurality of nitride semiconductor devices of claim 1 , wherein the high-temperature annealing is performed in a nitrogen atmosphere, in a hydrogen atmosphere or in a heavy hydrogen atmosphere.

3. The method of manufacturing the wafer comprising a plurality of nitride semiconductor devices of claim 1 , further comprising:
dividing a wafer on which the transistors are formed into individual semiconductor chips; and
building the semiconductor chip into a package,
wherein the high-temperature annealing is performed after building the semiconductor chip into the package.

4. The method of manufacturing the wafer comprising a plurality of nitride semiconductor devices of claim 1 , further comprising:
after the high-temperature annealing, dividing a wafer on which the transistors are formed into individual semiconductor chips; and
building the semiconductor chip into a package.

5. The method of manufacturing the wafer comprising a plurality of nitride semiconductor devices of claim 1 , further comprising, after the RF burn-in, performing high-temperature off-biasing at 125 to 250° C. for 1 to 96 hours by applying a gate voltage of −20 to −2 V to the gate electrode so that an off state is maintained.

6. A method of manufacturing a wafer comprising a plurality of nitride semiconductor devices comprising:
forming a transistor having a gate electrode Schottky-joined to a nitride semiconductor layer;
applying 3 to 1000 temperature cycles in a range from −65 to 360° C. to the transistor; and
after the temperature cycles, performing RF burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° C.,
wherein the RF burn-in reduces a leak current of the Schottky-joined gate electrode, which is present after the temperature cycles prior to the RF burn-in.

7. The method of manufacturing the wafer comprising a plurality of nitride semiconductor devices of claim 1 ,
wherein the RF burn-in is performed at a lower temperature than the high-temperature anneal.

8. The method of manufacturing the wafer comprising a plurality of nitride semiconductor devices of claim 6 ,
wherein the RF burn-in is performed at a lower temperature than the high-temperature anneal.

Assignees

• Mitsubishi Electric Corp

Inventors

• Sasaki Hajime

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/904

  of Group III-V semiconductors · CPC title

• H01L29/7786

  Electricity · mapped topic

• H01L29/66462 Primary

  Electricity · mapped topic

• H01L21/324

  Electricity · mapped topic