Two-terminal non-volatile memory cell for decoupled read and write operations

Patent metadata

Field	Value
Publication number	US-11568927-B2
Application number	US-202117217767-A
Country	US
Kind code	B2
Filing date	Mar 30, 2021
Priority date	Mar 30, 2021
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.

First claim

What is claimed is:

1. A memory structure comprising:
a first terminal connected to a first contact;
a second terminal connected to a second contact and a third contact;
a multi-level nonvolatile electrochemical cell, wherein the first contact and the second contact are connected to a variable resistance channel of the multi-level nonvolatile electrochemical cell, and wherein the third contact is connected to a programming gate of the multi-level nonvolatile electrochemical cell.

2. The structure of claim 1 , wherein the programming gate comprises an ion exchange layer located on the variable resistance channel.

3. The structure of claim 1 , wherein the programming gate comprises a metal-containing reservoir.

4. The structure of claim 2 , wherein a material of the ion exchange layer comprises a metal oxide.

5. The structure of claim 4 , wherein the metal oxide is selected from a group consisting of: HfOx and TaOx.

6. The structure of claim 1 , wherein a material for the variable resistance channel is selected from a group consisting of: WOx, TiOx, VOx, TaOx, HfOx.

7. The structure of claim 3 , wherein a material of the reservoir is a metal-oxide is selected form the group consisting of: CeO x , WO x , TiO x , CuOx, AlO x , TaO x , and HfO x .

8. A method of writing to a memory structure comprising:
creating a voltage between a first terminal and a second terminal of a multi-level nonvolatile electrochemical cell,
wherein the voltage causes electrons to move through a variable resistance channel of the multi-level nonvolatile electrochemical cell,
wherein the voltage causes an electric field across a charge-exchange layer thereby causing ions to move along that electric field in the multi-level nonvolatile electrochemical cell, and
wherein a direction of movement of ions across the charge-exchange layer is different from the direction of movement of electrons along the variable resistance channel.

9. The method of claim 8 , wherein the charge exchange layer comprises a metal oxide layer located in contact with the variable resistance channel.

10. The method of claim 8 , wherein the charge exchange layer further includes a metal containing reservoir layer.

11. The method of claim 10 , wherein the first terminal is connected to a first contact in contact with a first portion of the variable resistance channel, wherein the second terminal is connected to a second contact and a third contact, wherein the second contact is in contact with a second portion of the variable resistance channel, and wherein the third contact is attached at an opposite surface of the charge exchange layer from the variable resistance channel.

12. A method of reading a memory structure comprising:
creating a voltage between a first terminal and a second terminal of a multi-level nonvolatile electrochemical cell,
wherein the first terminal is connected to a first contact of the multi-level nonvolatile electrochemical cell,
wherein the second terminal is connected to a second contact and a third contact of the multi-level nonvolatile electrochemical cell,
wherein the voltage causes electrons to move through a variable resistance channel of the multi-level nonvolatile electrochemical cell, and
wherein the voltage causes an electric field across a charge-exchange layer of the multi-level nonvolatile electrochemical cell, and wherein the voltage is not sufficient enough to cause movement of ions into the variable resistance channel.

13. The method of claim 12 , wherein the charge-exchange layer comprises a metal oxide layer located in contact with the variable resistance channel.

14. The method of claim 12 , wherein the charge-exchange layer further includes a metal containing reservoir layer.

15. The method of claim 12 , wherein the first terminal is connected to the first contact in contact with a first portion of the variable resistance channel, wherein the second terminal is connected to the second contact and the third contact, wherein the second contact is in contact with a second portion of the variable resistance channel, and wherein the third contact is attached at an opposite surface of the charge exchange layer from the variable resistance channel.

16. A memory structure comprising:
a first terminal connected to a first contact;
a second terminal connected to a second contact and a third contact;
a multi-level nonvolatile electrochemical cell, wherein the first contact and the second contact are connected to a variable resistance channel of the multi-level nonvolatile electrochemical cell, and wherein the third contact is connected to a programming gate of the multi-level nonvolatile electrochemical cell,
wherein read and write operations pass between the first terminal and the second terminal through the multi-level nonvolatile electrochemical cell, and wherein a path of the read operation and a path of the write operation are different.

17. The structure of claim 16 , wherein the programming gate comprises an ion exchange layer located on the variable resistance channel.

18. The structure of claim 16 , wherein the programming gate comprises a metal-containing reservoir.

19. The structure of claim 17 , wherein a material of the ion exchange layer comprises a metal oxide.

20. The structure of claim 19 , wherein the metal oxide is selected from a group consisting of: HfOx and TaOx.

21. The structure of claim 16 , wherein a material for the variable resistance channel is selected from a group consisting of: WOx, TiOx, VOx, TaOx, HfOx.

22. The structure of claim 18 , wherein a material of the reservoir is a metal-oxide is selected form the group consisting of: CeO x , WO x , TiO x , CuOx, AlO x , TaO x , and HfO x .

23. The structure of claim 16 , wherein the path of the write operation occurs between the programming gate and the variable resistance channel.

24. The structure of claim 16 , wherein a path of the read operation occurs along the variable resistance channel.

Assignees

• IBM

Inventors

• Rozen John
• Kim Seyoung
• Solomon Paul Michael

Classifications

• G11C2013/0071

  Write using write potential applied to access device gate · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0011

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title

• H01L45/085

  Electricity · mapped topic

• G11C13/0069

  Writing or programming circuits or methods · CPC title