Gate driving unit circuit and method of driving the same, gate driving circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-11568775-B2
Application number	US-201816098046-A
Country	US
Kind code	B2
Filing date	Jan 29, 2018
Priority date	Jul 7, 2017
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

The present application provides a gate driving unit circuit and a method of driving the same, a gate driving circuit and a display apparatus. The gate driving unit circuit includes a shift register and a plurality of driving signal output sub-circuits. Each driving signal output sub-circuit corresponds to one of gate lines on an array substrate, is coupled to a first power supply terminal and a signal output terminal of the shift register, and also coupled to a corresponding one of driving scan signal lines. Each driving signal output sub-circuit is configured to output, under the control of a signal output by the signal output terminal of the shift register, a driving scan signal provided by the corresponding driving scan signal line or an OFF voltage provided by the first power supply terminal to the corresponding gate line.

First claim

What is claimed is:

1. A gate driving unit circuit, comprising:
a shift register and a plurality of driving signal output sub-circuits,
wherein each of the driving signal output sub-circuits is coupled to a corresponding one of a plurality of gate lines on an array substrate, coupled to a first power supply terminal and a signal output terminal of the shift register, and coupled to a corresponding and different one of driving scan signal lines, and time periods in which respective driving scan signals provided by the driving scan signal lines are of an ON voltage do not overlap with each other, and
each of the driving signal output sub-circuits is configured to output, under control of a signal output by the signal output terminal of the shift register, a driving scan signal provided by the corresponding one of the driving scan signal lines or an OFF voltage provided by the first power supply terminal to the corresponding one of the gate lines,
wherein the shift register comprises a pre-charge reset sub-circuit, a pulling-down node control sub-circuit, an output control sub-circuit and an output reset sub-circuit, the pre-charge reset sub-circuit, the pulling-down node control sub-circuit and the output control sub-circuit being coupled to a pulling-up node, and the output control sub-circuit and the output reset sub-circuit being coupled to a pulling-down node,
wherein the pre-charge reset sub-circuit is configured to perform a pre-charge processing on the pulling-up node under control of a pre-charge signal input by a pre-charge signal input terminal and a reset processing on the pulling-up node under control of a reset signal input by a reset signal input terminal,
the output control sub-circuit is coupled to a first clock signal terminal, and configured to transmit a first clock signal provided by the first clock signal terminal to the signal output terminal under control of a voltage level at the pulling-up node,
the pulling-down node control sub-circuit is coupled to a second clock signal terminal, and configured to transmit a second clock signal provided by the second clock signal terminal to the pulling-down node under control of the voltage level at the pulling-up node,
the output reset sub-circuit is configured to reset the signal output terminal under control of a voltage level at the pulling-down node,
the first clock signal and the second clock signal have a same period and a phase difference of a half of a period,
wherein the shift register further comprises a voltage synchronization sub-circuit which comprises a fourth transistor and a first capacitor,
a control electrode of the fourth transistor is coupled to the pulling-up node, a first electrode of the fourth transistor is coupled to a second power supply terminal, and a second electrode of the fourth transistor is coupled to a first end of the first capacitor at a voltage synchronization node,
a second end of the first capacitor is coupled to the first clock signal terminal, and
wherein the number of the driving signal output sub-circuits is six.

2. The gate driving unit circuit of claim 1 , wherein the voltage synchronization sub-circuit further comprises a fifth transistor, a control electrode of the fifth transistor is coupled to the second clock signal terminal, a first electrode of the fifth transistor is coupled to the second power supply terminal, and a second electrode of the fifth transistor is coupled to the voltage synchronization node.

3. The gate driving unit circuit of claim 1 , wherein the driving signal output sub- circuit comprises a first transistor and a second transistor,
a control electrode of the first transistor is coupled to the signal output terminal of the shift register, a first electrode of the first transistor is coupled to the corresponding one of the driving scan signal lines, and a second electrode of the first transistor is coupled to the corresponding one of the gate lines, and
a control electrode of the second transistor is coupled to the voltage synchronization node, a first electrode of the second transistor is coupled to the first power supply terminal, and a second electrode of the second transistor is coupled to the corresponding one of the gate lines.

4. The gate driving unit circuit of claim 3 , wherein the driving signal output sub-circuit further comprises a third transistor, and
a control electrode of the third transistor is coupled to the second clock signal terminal, a first electrode of the third transistor is coupled to the first power supply terminal, and a second electrode of the third transistor is coupled to the corresponding one of the gate lines.

5. The gate driving unit circuit of claim 1 , wherein the plurality of driving signal output sub-circuits are arranged in a column direction.

6. A gate driving circuit, comprising N cascaded stages of gate driving unit circuits, each of the gate driving unit circuits being the gate driving unit circuit of claim 1 , where N is an integer greater than or equal to two,
the signal output terminal of the shift register of each of a first stage to a (N−1)-th stage of gate driving unit circuits, among the N cascaded stages of gate driving unit circuits, is coupled to the pre-charge signal input terminal of the shift register of a subsequent stage of gate driving unit circuit, among the N cascaded stages of gate driving unit circuits, and
the signal output terminal of the shift register of each of a second stage to a N-th stage of gate driving unit circuits, among the N cascaded stages of gate driving unit circuits, is coupled to the reset signal input terminal of the shift register of a previous stage of gate driving unit circuit, among the N cascaded stages of gate driving unit circuits.

7. A display apparatus, comprising the gate driving circuit of claim 6 .

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Guangxing
• Zhang Kan
• Zhang Bin
• Chen Pengming
• Dong Dianzheng
• Zhang Qiang
• Xu Wenpeng
• Lu Heng

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title