Display panel

Patent metadata

Field	Value
Publication number	US-2016189683-A1
Application number	US-201514644977-A
Country	US
Kind code	A1
Filing date	Mar 11, 2015
Priority date	Dec 30, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A display panel including a pixel array and a gate driver circuit is provided. The pixel array has a plurality of pixels. The gate driver circuit is used for providing a plurality of gate signals to the pixels and includes a plurality of shift registers and a plurality of demultiplexers. The shift registers respectively receive a first gate signal of the gate signals and a first clock signal of a plurality of clock signals to respectively provide a first control signal and a second control signal. The demultiplexers respectively receive a plurality of second clock signals of the clock signals, respectively turn-on according to the first control signal provided by the corresponding one of the shift registers, and respectively cut-off according to the second control signal provided by the corresponding one of the shift registers.

First claim

What is claimed is:

1 . A display panel, comprising:
a pixel array, having a plurality of pixels; a gate driver circuit, coupled with the pixels to provide a plurality of gate signals, comprising:
a plurality of shift registers, respectively receiving a first gate signal of the gate signals and a first clock signal of a plurality of clock signals, to respectively provide a first control signal and a second control signal, wherein the clock signals are sequentially enabled; and
a plurality of demultiplexers, respectively receiving a plurality of second clock signals of the clock signals, and are coupled to the corresponding one of the shift registers to receive the first control signal and the second control signal provided by the corresponding one of the shift registers, wherein each of the demultiplexers are turned-on according to the first control signal provided by the corresponding one of the shift registers, to provide the gate signals according to the second clock signals, and each of the demultiplexers are cut-off according to the second control signal provided by the corresponding one of the shift registers.

2 . The display panel as claimed in claim 1 , wherein each of the shift registers comprises:
a first control circuit, receiving the first gate signal and the first clock signal, to enable the first control signal according to the first gate signal, and disable the first control signal according to the first clock signal, wherein an enabled period of the first gate signal does not overlap with an enabled period of the corresponding one of the second clock signal; and a second control circuit, receiving the first gate signal and the first clock signal, to disable the second control signal according to the first gate signal, and enable the second control signal according to the first clock signal.

3 . The display panel as claimed in claim 2 , wherein the first control circuit comprises:
a first transistor, having a first end receiving a forward scan voltage, a second end providing the first control signal, and a control end receiving the first gate signal; and a second transistor, having a first end receiving a gate low voltage, a second end coupled to the second end of the first transistor, and a control end receiving the first clock signal.

4 . The display panel as claimed in claim 3 , wherein the first control circuit further comprises:
a third transistor, having a first end receiving a backward scan voltage, a second end coupled to the second end of the first transistor, and a control end receiving a second gate signal of the gate signals, wherein the forward scan voltage is different than the backward scan voltage, and an enabled period of the second gate signal does not overlap with the enabled period of the corresponding one of the second clock signals.

5 . The display panel as claimed in claim 2 , wherein the second control circuit comprises:
a forth transistor, having a first end receiving a backward scan voltage, a second end providing the second control signal, and a control end receiving the first gate signal; a fifth transistor, having a first end receiving a gate high voltage, a second end coupled to the second end of the fourth transistor, and a control end receiving the first clock signal; and a first capacitor, coupled between a gate low voltage and the second end of the fourth transistor.

6 . The display panel as claimed in claim 5 , wherein the second control circuit further comprises:
a sixth transistor, having a first end receiving a forward scan voltage, a second end coupled to the second end of the fourth transistor, and a control end receiving a second gate signal of the gate signals, wherein the forward scan voltage is different than the backward scan voltage, and an enabled period of the second gate signal does not overlap with an enabled period of the corresponding one of the second clock signals.

7 . The display panel as claimed in claim 1 , wherein each of the demultiplexers comprises:
a plurality of signal transmitting units, receiving the second clock signals, the first control signal and the second control signal, wherein the signal transmitting units turn-on at the same time according to the first control signal, to output the second clock signals as the corresponding ones of the gate signals, and the signal transmitting units are cut-off at the same time according to the second control signal.

8 . The display panel as claimed in claim 7 , wherein each of the signal transmitting units comprises:
a seventh transistor, having a first end receiving the first control signal, a second end, and a control end receiving a gate high voltage; an eighth transistor, having a first end receiving the corresponding one of the second clock signals, a second end providing the corresponding one of the gate signals, and a control end coupled to the second end of the seventh transistor; a second capacitor, coupled between the control end of the eighth transistor and the second end of the eighth transistor; and a ninth transistor, having a first end coupled to the second end of the eighth transistor, a second end receiving a gate low voltage, and a control end receiving the second control signal.

9 . The display panel as claimed in claim 1 , wherein the second clock signals received by each of the demultiplexers are different than the first clock signal received by the corresponding one of the shift register.

10 . The display panel as claimed in claim 1 , wherein a first number of the clock signals and a second number of the second clock signals received by each of the demultiplexers are mutually prime numbers.

Assignees

• Chunghwa Picture Tubes Ltd

Inventors

• Chen Yi-Kai
• Tsai Chi-Chung
• Liu En-Chih
• Chen Ying-Hui
• Huang Yen-Yu

Classifications

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G5/18 Primary

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title