Shift register unit and method for driving the same, corresponding gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-10127995-B2
Application number	US-201615526315-A
Country	US
Kind code	B2
Filing date	May 30, 2016
Priority date	Mar 22, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

The disclosure discloses a shift register and a method for driving the same, a corresponding gate driving circuit and a display device. In the shift register, a pull-up driving unit is connected with a pull-up unit via a pull-up node, a discharge auxiliary unit is used for pulling low the potential of the pull-up node according to a discharge control signal, a discharge driving unit is used for pulling high the potential of a gate line connected with the signal output terminal of the shift register according to the discharge control signal, and a reset unit is further used for pulling low again the potential of the gate line connected with the signal output terminal of the shift register, after the discharge driving unit pulls high the potential of the gate line and the outputting of it finishes.

First claim

The invention claimed is:

1. A shift register comprising a pull-up driving unit, a pull-up unit, a pull-down unit, a pull-down driving unit and a reset unit, the pull-up driving unit being connected with the pull-up unit via a pull-up node, the reset unit being used for pulling low the potential of a gate line connected with a signal output terminal of the shift register after normal outputting by the shift register finishes, wherein the shift register further comprises a discharge auxiliary unit, a discharge driving unit and a discharge control signal terminal, wherein
the discharge auxiliary unit is used for pulling low the potential of the pull-up node according to a discharge control signal inputted by the discharge control signal terminal,
the discharge driving unit is used for pulling high the potential of the gate line connected with the signal output terminal of the shift register according to the discharge control signal inputted by the discharge control signal terminal, and
the reset unit is further used for pulling low again the potential of the gate line connected with the signal output terminal of the shift register, after the discharge driving unit pulls high the potential of the gate line connected with the signal output terminal of the shift register and the outputting of it finishes.

2. The shift register as claimed in claim 1 , wherein the discharge auxiliary unit comprises a thirteenth thin film transistor, the gate of the thirteenth thin film transistor is connected with the discharge control signal terminal, the drain of the thirteenth thin film transistor is connected with the pull-up node, and the source of the thirteenth thin film transistor is electrically connected with a low level signal terminal.

3. The shift register as claimed in claim 1 , wherein the discharge driving unit comprises a fourteenth thin film transistor, the gate of the fourteenth thin film transistor is electrically connected with the discharge control signal terminal, the drain of the fourteenth thin film transistor is electrically connected with a first clock signal terminal, and the source of the fourteenth thin film transistor is electrically connected with the signal output terminal.

4. The shift register as claimed in claim 1 , wherein
the pull-up driving unit comprises a first thin film transistor and a second thin film transistor, the gate and the drain of the first thin film transistor and the drain of the second thin film transistor are electrically connected with a trigger signal terminal, the source of the first thin film transistor and the source of the second thin film transistor are electrically connected with the pull-up node, and the gate of the second thin film transistor is electrically connected with a second clock signal terminal,
the pull-up unit comprises a third thin film transistor and a capacitor, the gate of the third thin film transistor and a first terminal of the capacitor are electrically connected with the pull-up node, the drain of the third thin film transistor is electrically connected with a first clock signal terminal, and the source of the third thin film transistor and a second terminal of the capacitor are electrically connected with the signal output terminal,
the pull-down unit comprises a fourth thin film transistor, a fifth thin film transistor and a sixth thin film transistor, the gate of the fourth thin film transistor and the gate of the fifth thin film transistor are electrically connected with the pull-down node, the drain of the fourth thin film transistor is electrically connected with the pull-up node, the source of the fourth thin film transistor, the source of the fifth thin film transistor and the source of the sixth thin film transistor are electrically connected with a low level signal terminal, the drain of the fifth thin film transistor and the drain of the sixth thin film transistor are electrically connected with the signal output terminal, and the gate of the sixth thin film transistor is electrically connected with the second clock signal terminal,
the pull-down driving unit comprises a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor and a tenth thin film transistor, the gate and the drain of the seventh thin film transistor and the drain of the eighth thin film transistor are electrically connected with the second clock signal terminal, the source of the seventh thin film transistor, the gate of the eighth thin film transistor and the drain of the ninth thin film transistor are electrically connected, the source of the eighth thin film transistor and the drain of the tenth thin film transistor are electrically connected with the pull-down node, the gate of the ninth thin film transistor and the gate of the tenth thin film transistor are electrically connected with the pull-up node, and the source of the ninth thin film transistor and the source of the tenth thin film transistor are electrically connected with the low level signal terminal, and
the reset unit comprises an eleventh thin film transistor and a twelfth thin film transistor, the gate of the eleventh thin film transistor and the gate of the twelfth thin film transistor are electrically connected with a reset signal terminal, the drain of the eleventh thin film transistor is electrically connected with the pull-up node, the source of the eleventh thin film transistor and the source of the twelfth thin film transistor are electrically connected with the low level signal terminal, and the drain of the twelfth thin film transistor is electrically connected with the signal output terminal.

5. The shift register as claimed in claim 4 , wherein all of the above thin film transistors are N-type thin film transistors.

6. A gate driving circuit, comprising a plurality of cascaded shift registers, wherein the shift registers are shift registers as claimed in claim 1 .

7. The gate driving circuit as claimed in claim 6 , wherein it further comprises a discharge control signal line for providing the discharge control signal terminal of the shift register with the discharge control signal to control the discharge auxiliary unit and the discharge driving unit, and
the discharge control signal is kept at a low level during the scanning by the gate driving circuit, and provides a high level of a clock cycle after the scanning by the gate driving circuit finishes, which clock cycle is the cycle of a clock signal in the shift register.

8. A display device, comprising the gate driving circuit as claimed in claim 7 .

9. A display device, comprising the gate driving circuit as claimed in claim 6 .

10. A method for driving a shift register, which is used for driving a shift register as claimed in claim 1 , wherein it comprises:
providing a first clock signal, a second clock signal, an initial trigger signal, a low level signal, a reset signal and the discharge control signal by a first clock signal terminal, a second clock signal terminal, a trigger signal terminal, a low level signal terminal, a reset signal terminal and the discharge control signal terminal in a one-to-one correspondence relationship, wherein
the first clock signal and the second clock signal are complementary pulse signals, the initial trigger signal has two trigger high level pulses which are spaced and identical to two clock high level pulses of the second clock signal having the same interval, the reset signal has two reset high level pulses which are spaced, the former one of the reset high level pulses falls behind the former one of the trigger high level pulses of the initial trigger signal by one clock cycle, and the latter one of the reset high level pulses is synchronized to the latter one of the trigger high le

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Chen Mo
• Zhao Jian

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3674 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title