Shift register unit, gate driver circuit and display device

Patent metadata

Field	Value
Publication number	US-10311795-B2
Application number	US-201615325137-A
Country	US
Kind code	B2
Filing date	Aug 9, 2016
Priority date	Jan 5, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A shift register unit is disclosed which includes an input module, a reset module, a node control module, a first output module and a second output module. Each of the shift register units can output two scan signals that have a phase difference with respect to each other. Also disclosed are a gate driver circuit and a display device.

First claim

What is claimed is:

1. A shift register unit comprising:
an input terminal, a reset terminal, a reference terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first output terminal, a second output terminal,
an input circuit for receiving an input signal from the input terminal and providing the input signal to a first node as a first level voltage;
a first reset circuit for receiving a reference voltage from the reference terminal, and providing the reference voltage to the first node as a second level voltage in response to a reset signal from the reset terminal, the second level voltage being logically opposite to the first level voltage;
a node control circuit for receiving a third clock signal from the third clock terminal and the reference voltage, and providing at a second node a second voltage signal logically opposite to a first voltage signal at the first node, the first voltage signal comprising a portion having the first level voltage and a portion having the second level voltage;
a first output circuit for receiving a first clock signal from the first clock terminal and the reference voltage, and selectively providing the first clock signal or the reference voltage to the first output terminal in response to first voltage signal and the second voltage signal; and
a second output circuit for receiving a second clock signal from the second clock terminal and the reference voltage, selectively providing the second clock signal or the reference voltage to the second output terminal in response to the first voltage signal and the second voltage signal, and maintaining a voltage difference between the first node and the second output terminal when the first node is floated,
wherein the node control circuit comprises:
a first node control circuit for providing the reference voltage to the first node in response to the second voltage signal; and
a second node control circuit for providing at the second node the second voltage signal in response to the third clock signal and the first voltage signal.

2. The shift register unit of claim 1 , wherein the first clock signal and the second clock signal have a phase difference of 90° with respect to each other, and wherein the third clock signal and the second clock signal have phases opposite to each other.

3. A gate driver circuit comprising a plurality of shift register units as recited in claim 2 that are cascaded with each other, wherein
the input terminal of the first stage of shift register unit is configured to receive a start signal;
the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and
the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit.

4. The shift register unit of claim 1 , wherein the first node control circuit comprises a seventh transistor having a source connected to the reference terminal, a gate connected to the second node, and a drain connected to the first node.

5. A gate driver circuit comprising a plurality of shift register units as recited in claim 4 that are cascaded with each other, wherein
the input terminal of the first stage of shift register unit is configured to receive a start signal;
the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and

the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit.

6. The shift register unit of claim 1 , wherein the second node control circuit comprises:
an eighth transistor having a source and a gate jointly connected to the third clock terminal, and a drain;
a ninth transistor having a source connected to the third clock terminal, a gate connected to the drain of the eighth transistor, and a drain connected to the second node;
a tenth transistor having a source connected to the reference terminal, a gate connected to the first node, and a drain connected to the drain of the eighth transistor; and
an eleventh transistor having a source connected to the reference terminal, a gate connected to the first node, and a drain connected to the second node.

7. The shift register unit of claim 1 , wherein the input circuit comprises a first transistor having a source and a gate jointly connected to the input terminal and a drain connected to the first node.

8. A gate driver circuit comprising a plurality of shift register units as recited in claim 4 that are cascaded with each other, wherein
the input terminal of the first stage of shift register unit is configured to receive a start signal;
the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and
the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit.

9. The shift register unit of claim 1 , wherein the first reset circuit comprises a second transistor having a source connected to the reference terminal, a gate connected to the reset terminal, and a drain connected to the first node.

10. A gate driver circuit comprising a plurality of shift register units as recited in claim 9 that are cascaded with each other, wherein
the input terminal of the first stage of shift register unit is configured to receive a start signal;
the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and
the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit.

11. The shift register unit of claim 1 , wherein the first output circuit comprises:
a third transistor having a source connected to the first clock terminal, a gate connected to the first node, and a drain connected to the first output terminal; and
a fourth transistor having a source connected to the reference terminal, a gate connected to the second node, and a drain connected to the first output terminal.

12. A gate driver circuit comprising a plurality of shift register units as recited in claim 11 that are cascaded with each other, wherein
the input terminal of the first stage of shift register unit is configured to receive a start signal;
the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and
the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit.

13. The shift register unit of claim 1 , wherein the second output circuit comprises:
a fifth transistor having a source connected to the second clock terminal, a gate connected to the first node, and a drain connected to the second output terminal;
a sixth transistor having a source connected to the reference terminal, a gate connected to the second node, and a drain connected to the second output terminal; and
a

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Chen Huabin
• Wang Ruirui
• Gao Yingqiang
• Cui Xiaopeng

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/061

  for resetting or blanking · CPC title