Memory device including interface circuit for data conversion according to different endian formats

Patent metadata

Field	Value
Publication number	US-11567692-B2
Application number	US-202117213732-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	May 19, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

First claim

What is claimed is:

1. A memory device comprising:
a memory bank;
a processing element (PE) coupled to the memory bank and configured to perform computation processing;
a serializer/deserializer (SERDES) region comprising a SERDES configured to perform an operation of parallelizing a serial data stream received from a host device external to the memory device, and perform an operation of serializing a parallel data stream output from the memory bank or the PE; and
an interface circuit comprising a data transfer path related to the memory bank, the PE, and the SERDES, and configured to allow the memory device to perform data conversion in the data transfer path based on a control signal set in accordance with an endian format of the host device,
wherein the endian format of the host is one of a big-endian format in which a first byte of date in the data transfer path is ordered before a second byte of the data in the date transfer path, and a little-endian format in which the second byte is ordered before the first byte.

2. The memory device of claim 1 , wherein the interface circuit comprises:
a first input data bus configured to receive a first byte;
a second input data bus configured to receive a second byte;
a control signal line configured to receive the control signal;
a first output data bus;
a second output data bus; and
a data bus converter connected to the first and second input data buses, the control signal line, and the first and second output data buses,
wherein the data bus converter is configured to, in response to a first logic state of the control signal, pass the first byte of the first input data bus to the first output data bus and pass the second byte of the second input data bus to the second output data bus, and, in response to a second logic state opposite to the first logic state of the control signal, reconfigure and transfer the first byte of the first input data bus to the second output data bus and reconfigure and transfer the second byte of the second input data bus to the first output data bus.

3. The memory device of claim 2 , further comprising a memory physical layer interface (PHY) region configured to communicate with the host device,
wherein the interface circuit is disposed between the memory PHY region and the SERDES region, and is configured such that
when data is input from the host device to the memory device, the first and second input data buses are coupled to the memory PHY region, and the first and second output data buses are coupled to the SERDES region, and
when the data is output from the memory device to the host device, the first and second input data buses are coupled to the SERDES region, and the first and second output data buses are coupled to the memory PHY region.

4. The memory device of claim 2 , wherein the interface circuit is between the SERDES region and the memory bank or the PE, and is configured such that
when data is input from the host device to the memory device, the first and second input data buses are coupled to the SERDES region, and the first and second output data buses are coupled to the memory bank or the PE, and
when the data is output from the memory device to the host device, the first and second input data buses are coupled to the memory bank or the PE, and the first and second output data buses are coupled to the SERDES region.

5. The memory device of claim 2 , further comprising:
a bank group comprising a plurality of memory banks;
a bank group input/output line coupled to the bank group to transfer data between the host device external to the memory device and the bank group;
a first bank local input/output line coupled to a first memory bank configured to transfer data provided to the first memory bank and data read from the first memory bank; and
a second bank local input/output line coupled to a second memory bank configured to transfer data provided to the second memory bank and data read from the second memory bank.

6. The memory device of claim 5 , wherein the PE is shared by the first and second memory banks,
wherein the interface circuit is between the SERDES region and the bank group input/output line, and is configured that
when data is input from the host device to the memory device, the first and second input data buses are coupled to the SERDES region, and the first and second output data buses are coupled to the bank group input/output line, and
when the data is output from the memory device to the host device, the first and second input data buses are coupled to the bank group input/output line, and the first and second output data buses are coupled to the SERDES region.

7. The memory device of claim 5 , further comprising:
a first PE coupled to the first memory bank; and
a second PE coupled to the second memory bank,
wherein the interface circuit is between the first PE and the first bank local input/output line, and between the second PE and the second bank local input/output lines, and is configured such that
when data is input from the host device to the memory device, the first and second input data buses are coupled to the first and second PEs, respectively, and the first and second output data buses are coupled to the first and second bank local input/output lines respectively, and
when the data is output from the memory device to the host device, the first and second input data buses are coupled to the first and second bank local input/output lines respectively, and the first and second output data buses are coupled to the first and second PEs respectively.

8. The memory device of claim 1 , wherein the control signal is provided in a mode register set (MRS) of the memory device or provided according to a state of a nonvolatile memory device inside the memory device.

9. The memory device of claim 1 , wherein the memory device is a high bandwidth memory (HBM) further comprising:
a buffer die comprising the SERDES region; and
a dynamic random access memory (DRAM) die comprising the memory bank and the PE.

10. A memory device comprising:
a memory bank;
a serializer/deserializer (SERDES) region comprising a SERDES configured to perform an operation of parallelizing a serial data stream received from a host device external to the memory device, and perform an operation of serializing a parallel data stream output from the memory bank; and
an interface circuit comprising a data transfer path related to the memory bank and the SERDES, coupled to the SERDES region, and configured to allow the memory device to perform data conversion in the data transfer path based on a control signal set in accordance with an endian format of the host device,
wherein the endian format of the host is one of a big-endian format in which a first byte of date in the data transfer path is ordered before a second byte of the data in the date transfer path, and a little-endian format in which the second byte is ordered before the first byte.

11. The memory device of claim 10 , wherein the interface circuit comprises:
first data lines through which first data bits of a first endian format are transferred;
a control signal line configured to receive the control signal;
second data lines; and
a data converter connected to the first data lines, the control signal line, and the second data lines,
wherein the data converter is configured to, in response to a first logic state of the control signal, pass the first data bits of the first data lines to the second data lines in the first endian format and, in response to a second logic state opposite to the first logic state of the control signal, reconfigure the first data bits of the first data lines to a second endian format di

Assignees

• Samsung Electronics Co Ltd

Inventors

• O Seongil
• Son Jongpil
• Sohn Kyomin

Classifications

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0661 Primary

  Format or protocol conversion arrangements · CPC title

• G06F13/387

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title