Dual master JTAG method, circuit, and system

Patent metadata

Field	Value
Publication number	US-9323633-B2
Application number	US-201313852223-A
Country	US
Kind code	B2
Filing date	Mar 28, 2013
Priority date	Mar 28, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode. An instruction decoder and multiplexer circuit applies control signals from the selection multiplexer to control the JTAG data registers.

First claim

What is claimed is:

1. A dual-master controller, comprising:
a plurality of JTAG data registers including a controller-mode register configured to store information indicating either a standard JTAG or a processor-controlled mode of operation;
a JTAG TAP controller adapted to receive control signals over a standard test access port;
a processor controller adapted to receive processor control signals over an external processor bus;
a selection multiplexer coupled to the standard access port and the external processor bus and coupled to the JTAG TAP controller and the processor controller, the selection multiplexer configured to output either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal;
a logic circuit coupled to the controller-mode register and coupled to the selection multiplexer and adapted to receive a force JTAG signal, the logic circuit configured to activate the JTAG mode selection signal responsive to the force JTAG signal being active or the information in the controller-mode register indicating the standard JTAG mode of operation, and configured to deactivate the JTAG mode selection signal responsive to the force JTAG signal being inactive or the information in the controller-mode register indicating the processor-controller mode of operation; and
an instruction decoder and multiplexer circuit coupled to the selection multiplexer and to the standard test access port, and coupled between the JTAG TAP controller and the JTAG data registers, the instruction decoder and multiplexer circuit configured to apply control signals from the selection multiplexer to control the JTAG data registers and to prevent the processor controller from accessing selected ones of the JTAG data registers.

2. The dual-master controller of claim 1 , wherein the processor controller comprises a state machine.

3. The dual-master controller of claim 1 , further comprising an endian circuit configured to change the endianness of read data output from the instruction decoder and multiplexer circuit.

4. The dual-master controller of claim 1 , wherein the controller-mode register stores a reset bit and a mode bit.

5. The dual-master controller of claim 1 , wherein the processor controller comprises:
a state machine adapted to be coupled to a command bus portion of the external processor bus and configured to generate control signals for controlling the data registers responsive to command signals on the command bus portion;
a serializer adapted to be coupled to a write bus portion of the external processor bus and operable responsive to the control signals to provide write test data applied on the write bus portion to the data registers; and
a de-serializer adapted to be coupled to a read bus portion of the external processor bus and operable responsive to the control signals to provide read test data from the data registers on the read bus portion.

6. The dual-master controller of claim 5 further comprising an endian circuit coupled between the de-serializer and the read bus portion and configured to change the endianness of read test data applied on the read bus portion responsive to the control signals from the state machine.

7. The dual-master controller of claim 6 further comprising an output multiplexer coupled between the data registers and the de-serializer.

8. The dual-master controller of claim 1 , wherein the plurality of JTAG data registers further include a bit scan register, an identification register, a bypass register, and additional user data registers.

9. The dual-master controller of claim 8 , wherein the bit scan register, an identification register, a bypass register, and controller-mode register are controlled only by the JTAG TAP controller.

10. The dual-master controller of claim 8 , wherein the instruction decoder and multiplexer circuit further comprises a JTAG TAP controller decoding circuit configured to decode signals from the standard test access port provided by the selection multiplexer.

11. The dual-master controller of claim 10 , wherein the instruction decoder and multiplexer circuit further comprises a processor decoding circuit configured to decode signals from the external processor bus provided by the selection multiplexer.

12. An electronic system, comprising:
core logic circuitry;
a plurality of JTAG data registers coupled to the core logic circuitry, the JTAG data registers including a controller-mode register configured to store information indicating either a standard JTAG or a processor-controlled mode of operation;
a dual-master controller, comprising,
a JTAG TAP controller adapted to receive control signals over a standard test access port;
a processor controller adapted to receive processor control signals over an external processor bus;
a selection multiplexer coupled to the standard access port and the external processor bus and coupled to the JTAG TAP controller and the processor controller, the selection multiplexer configured to output either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal;
a logic circuit coupled to the controller-mode register and coupled to the selection multiplexer and adapted to receive a force JTAG signal, the logic circuit configured to activate the JTAG mode selection signal responsive to the force JTAG signal being active or the information in the controller-mode register indicating the standard JTAG mode of operation, and configured to deactivate the JTAG mode selection signal responsive to the force JTAG signal being inactive or the information in the controller-mode register indicating the processor-controller mode of operation; and
an instruction decoder and multiplexer circuit coupled to the selection multiplexer and to the standard test access port, and coupled between the JTAG TAP controller and the JTAG data registers, the instruction decoder and multiplexer circuit configured to apply control signals from the selection multiplexer to control the JTAG data registers and to deny access by the processor controller to some of the JTAG data registers.

13. The electronic system of claim 12 , wherein the core logic comprises a microprocessor.

14. The electronic system of claim 12 , wherein the controller-mode register stores a reset bit and a mode bit.

15. The electronic system of claim 12 , wherein the processor controller comprises:
a state machine adapted to be coupled to a command bus portion of the external processor bus and configured to generate control signals for controlling the data registers responsive to command signals on the command bus portion;
a serializer adapted to be coupled to a write bus portion of the external processor bus and operable responsive to the control signals to provide write test data applied on the write bus portion to the data registers; and
a de-serializer adapted to be coupled to a read bus portion of the external processor bus and operable responsive to the control signals to provide read test data from the data registers on the read bus portion.

16. The electronic system of claim 15 wherein the dual-mode controller further comprises an endian circuit coupled between the de-serializer and the read bus portion and configured to change the endianness of read test data applied on the read bus portion responsive to the control signals from the state machine.

17. The electronic system of claim 12 wherein the dual-master controller further comprises an output multiplexer coupled between the data registers and the de-serializer.

Assignees

• St Microelectronics Inc

Inventors

• Brambilla Marco
• Lacour Ulderic
• Ozdemir Cecilia

Classifications

• G06F11/267 Primary

  Reconfiguring circuits for testing, e.g. LSSD, partitioning · CPC title