Microcomputer having processor capable of changing endian based on endian information in memory

Patent metadata

Field	Value
Publication number	US-10140207-B2
Application number	US-201815876780-A
Country	US
Kind code	B2
Filing date	Jan 22, 2018
Priority date	Apr 20, 2010
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing a program executed in user boot mode and corresponding endian information and a user area for storing a program executed in user mode and corresponding endian information. A data transfer circuit reads endian information stored in the user boot area or the user area in accordance with operation mode and supplies the endian information to a CPU before reset release of the CPU. Accordingly, an external terminal for endian selection can be eliminated.

First claim

What is claimed is:

1. A microcomputer comprising:
a processor comprising multiple operation modes including a reset mode, a first mode and a second mode,
an external terminal for setting the first mode or the second mode,
a nonvolatile memory, and
a data transfer circuit,
wherein the nonvolatile memory includes:
a first region including a third region in which first endian information for setting an endian mode of the processor is stored,
a second region including a fourth region in which second endian information for setting the endian mode of the processor is stored,

wherein an operation mode changes from the reset mode to the first mode when the external terminal enables the first mode,
wherein an operation mode changes from the reset mode to the second mode when the external terminal enables the second mode,
wherein, in the first mode, the data transfer circuit reads the first endian information from an address of the third region and outputs to the processor the first endian information and the processor succeedingly executes a first program stored in the first region,
wherein the first program located in the first region is not rewritable,
wherein, in the second mode, the data transfer circuit reads the second endian information from an address of the fourth region and outputs to the processor the second endian information and the processor succeedingly executes a second program stored in the second region,
wherein the second program located in the second region is rewritable, and
wherein the data transfer circuit outputs the first or the second endian information before a CPU reset signal goes to be high to release reset.

2. The microcomputer according to claim 1 ,
wherein the nonvolatile memory includes a fifth region including a sixth region in which third endian information for setting the endian mode of the processor is stored,
wherein the multiple operation modes further include a third mode,
wherein the operation mode changes from the reset mode to the third mode when the external terminal enables the third mode,
wherein, in the third mode, the data transfer circuit reads the third endian information from an address of the sixth region and outputs to the processor the third endian information and the processor succeedingly executes a third program stored in the fifth region.

3. The microcomputer according to claim 2 ,
wherein the data transfer circuit reads from the address of the third region or fourth region depending on the operation mode set by the external terminal after an internal reset signal goes to be high level to release reset.

4. The microcomputer according to claim 1 ,
wherein the data transfer circuit reads endian information from an address of the third region or fourth region and outputs the endian information to the processor after an internal reset signal goes to be high level to release reset,
wherein the processor operates with the endian information when the CPU reset signal of the processor is released.

5. The microcomputer according to claim 4 ,
wherein the processor is in the reset mode when the internal reset signal is asserted to be low level,
wherein the data transfer circuit reads the endian information from the address of the third region or the fourth region when the internal reset signal goes to be high level to release reset.

Assignees

• Renesas Electronics Corp

Inventors

• Sakugawa Mamoru
• Sakurai Tomohiro
• Watanabe Katsuyoshi
• Ikari Seiji
• Nasu Takashi
• Kumagai Tsutomu

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/4403

  Processor initialisation · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title