Systems and methods for managing endian mode of a device

Patent metadata

Field	Value
Publication number	US-9348784-B2
Application number	US-32587508-A
Country	US
Kind code	B2
Filing date	Dec 1, 2008
Priority date	Dec 1, 2008
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

Systems, methods, and devices for managing endian-ness are disclosed. In one embodiment, a device is configured to selectively operate in one of a big-endian operating mode or a little-endian operating mode. The device may include a register in which the current endian mode of the device is indicated in at least two different bit positions within the register. The at least two different bit positions may be chosen such that a data bit in one of the bit positions would be read by a system if the device and system operate in the same endian mode, while a data bit in another of the chosen bit positions would be read by the system if the device and system are operating in different endian modes from one another. In some embodiments, the endian mode of the device may be controlled by a hardware input or a software input.

First claim

What is claimed is:

1. A device comprising:
a register comprising a plurality of memory cells, the register configured to receive and store a plurality of data bits, wherein a current endian mode of the device is represented by a device endian mode indicator and a duplicate device endian mode indicator stored in at least two different locations of the register, wherein the device endian mode indicator and the duplicate device endian mode indicator are configured to indicate the current endian mode of the device regardless of an endian mode used to read the register; and
input/output circuitry configured to facilitate communication of the plurality of data bits from the device;
wherein the device is configured to power-on or reset to a default mode that enables reading of the register.

2. The device of claim 1 , wherein the device endian mode indicator and the duplicate device endian mode indicator are configured to enable a component receiving the plurality of data bits from the device to recognize the current endian mode of the device.

3. The device of claim 2 , wherein the device endian mode indicator and the duplicate device endian mode indicator represent the current endian mode of the device as a little-endian mode using a first bit value and represent the current endian mode of the device as a big-endian mode using a second bit value.

4. The device of claim 1 , wherein the device is configured to selectively operate in one of two different endian modes.

5. The device of claim 4 , wherein the device is configured to operate in a selected one of the two different endian modes in response to a signal received on a hardware input of the device.

6. The device of claim 5 , wherein the device is configured to enable a software override of the signal received on the hardware input.

7. The device of claim 6 , comprising a memory medium including executable routines configured to override the signal received on the hardware input.

8. The device of claim 6 , wherein the device is configured such that the software override is enabled in accordance with a software override data bit stored in a particular bit position of the register and/or in a particular bit position of an additional register.

9. The device of claim 8 , wherein the device is configured such that the current endian mode of the device is controlled in accordance with a software endian select bit if the software override is enabled.

10. The device of claim 9 , wherein the software endian select bit is stored in a bit position of the additional register.

11. The device of claim 1 , wherein the input/output circuitry is configured to connect to a data bus.

12. The device of claim 11 , wherein the data bus includes at least one of a synchronous dynamic random access memory bus, a double data rate memory bus, or some other multi-byte parallel bus.

13. The device of claim 1 , wherein the device includes a pattern recognition device.

14. A device comprising:
a plurality of registers configured to store an indication of a current endian mode of the device as represented by a device endian mode indicator and a duplicate device endian mode indicator stored in at least two different locations of a register of the plurality of registers, wherein the device endian mode indicator and the duplicate device endian mode indicator are configured to indicate the current endian mode of the device regardless of an endian mode used to read the register;
a register interface configured to read data from, and write data to, the plurality of registers, wherein the register interface is a hardware interface configured to selectively operate in one of a little-endian mode or a big-endian mode and to translate data read from and/or written to the plurality of registers based on a selected device endian mode; and
an endian mode hardware pin, wherein the register interface is configured to operate in a default endian mode based on a signal received on the endian mode hardware pin.

15. The device of claim 14 , wherein the device is configured to enable the default endian mode to be overridden for operation of the register interface in an endian mode different than the default endian mode.

16. The device of claim 15 , wherein a register of the plurality of registers includes a register bit for controlling override of the default endian mode.

17. A system comprising:
a processor;
a storage device including application instructions stored therein for execution by the processor; and
an additional device communicatively coupled to the processor by a data bus, wherein the additional device comprises a register, wherein a current endian mode of the device is represented by a device endian mode indicator and a duplicate device endian mode indicator stored in at least two different locations of the register, wherein the device endian mode indicator and the duplicate device endian mode indicator are configured to indicate the current endian mode of the device regardless of whether a particular endian mode or a different endian mode is used to read the register;
wherein the processor and the data bus are configured to operate in accordance with the particular endian mode and read the current endian mode of the additional device from one of the device endian mode indicator and the duplicate device endian mode in accordance with the particular endian mode.

18. The system of claim 17 , comprising a computer including the processor.

19. The system of claim 18 , wherein the additional device includes at least one of a router or a modem communicatively coupled to the computer.

20. The system of claim 18 , wherein the computer includes the storage device.

21. The system of claim 18 , wherein the computer includes the additional device.

22. The system of claim 17 , wherein the application instructions stored within the storage device include instructions for detecting the current endian mode of the additional device.

23. A method comprising:
accessing data stored in a register of a device, wherein a current endian mode of the device is represented by a device endian mode indicator and a duplicate device endian mode indicator stored in at least two different locations of the register, wherein the device endian mode indicator and the duplicate device endian mode indicator are configured to indicate the current endian mode of the device regardless of an endian mode used to read the register; and
determining the current endian mode of the device by reading, via a processor, the device endian mode indicator if the accessed data is read in accordance with a first endian mode, or by reading the duplicate device endian mode indicator if the accessed data is read in accordance with a second endian mode.

24. The method of claim 23 , comprising changing the endian mode of the device.

25. The method of claim 24 , wherein changing the endian mode of the device includes overriding, via software, a default endian mode.

26. The method of claim 25 , wherein overriding a default endian mode includes overriding a default endian mode selected by a signal on a hardware input of the device.

27. The method of claim 24 , wherein changing the endian mode of the device includes changing a value of the device endian mode indicator and the duplicate device endian mode indicator.

28. The method of claim 27 , comprising automatically setting the value via a software driver,

Assignees

• Noyes Harold B
• Micron Technology Inc

Inventors

• Noyes Harold B

Classifications

• G06F13/4013 Primary

  with data re-ordering, e.g. Endian conversion · CPC title

• G06K9/00986

  Physics · mapped topic

• G06F3/00 Primary

  Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06V10/955

  using specific electronic processors · CPC title