High speed data weighted averaging architecture

Patent metadata

Field	Value
Publication number	US-10050640-B1
Application number	US-201815864233-A
Country	US
Kind code	B1
Filing date	Jan 8, 2018
Priority date	Jan 8, 2018
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

First claim

The invention claimed is:

1. A circuit for generating a data weighted averaging signal from a thermometric code signal, comprising:
a crossbar switch matrix having an input configured to receive the thermometric code signal and an output configured to output the data weighted averaging signal, wherein switching between the input and output by the crossbar switch matrix is controlled by a crossbar selection signal; and
a control circuit configured to receive a previous time cycle of the data weighted averaging signal and determine from bits of the previous time cycle of the data weighted averaging signal a bit location within the previous time cycle of the data weighted averaging signal where an ending logic transition occurs and generate the crossbar selection signal to control switching between the input and output by the crossbar switch matrix to select a bit location within a current time cycle of the data weighted averaging signal where a beginning logic transition occurs.

2. The circuit of claim 1 , wherein the data weighted averaging signal comprises a plurality of bits and wherein the control circuit comprises a logic circuit configured to logically combine the plurality of bits of the data weighted averaging signal to detect the bit location of the data weighted averaging signal where the ending logic transition occurs.

3. The circuit of claim 2 , wherein the logic circuit comprises a plurality of AND gates, each AND gate having a first input coupled to receive one bit of the data weighted averaging signal and a second input coupled to receive another bit of the data weighted averaging signal, wherein said one bit and said another bit are adjacent bits within the data weighted averaging signal.

4. The circuit of claim 2 , wherein the logic circuit generates a selection input signal specifying the bit location of the data weighted averaging signal where the beginning logic transition occurs.

5. The circuit of claim 4 , wherein the control circuit further comprises a data storage circuit that stores the selection input signal in response to a load clock signal and outputs the crossbar selection signal.

6. The circuit of claim 5 , wherein the control circuit further comprises a clock generation circuit configured to generate said load clock signal.

7. The circuit of claim 6 , wherein the clock generation circuit comprises a detection circuit configured to detect an all logic 1 state for bits of the thermometric code signal and in response thereto disable generation of the load clock signal.

8. The circuit of claim 6 , wherein the clock generation circuit comprises a detection circuit configured to detect an all logic 0 state for bits of the thermometric code signal and in response thereto disable generation of the load clock signal.

9. The circuit of claim 1 , wherein the thermometric code signal includes a plurality of bits and wherein the data weighted averaging signal includes a plurality of bits, said crossbar switch matrix operating to selectively connect the bits of the thermometric code signal to the bits of the data weighted averaging signal in a sequence having a barrel shifted position specified by the crossbar selection signal.

10. The circuit of claim 9 , wherein the barrel shifted position places the bit location for the beginning logic transition for the current time cycle of the data weighted averaging signal adjacent to the bit location for the ending logic transition for the previous time cycle of the data weighted averaging signal.

11. A circuit, comprising:
an input data bus carrying a multi-bit input data word in thermometer coded format;
a crossbar switch matrix having switch inputs coupled to the input data bus to receive the multi-bit input data word and switch outputs configured to output a multi-bit output data word that is a data weighted averaging (DWA) conversion of the thermometer coded multi-bit input data word; and
a DWA control circuit configured to receive the multi-bit output data word and generate from the multi-bit output data word a multi-bit selection signal that is applied by a selection data bus to control inputs of the crossbar switch matrix;
wherein the crossbar switch matrix is configured to operate in response to the multi-bit selection signal to selectively map the switch inputs to the switch outputs to effectuate the DWA conversion of the thermometer coded multi-bit input data word to output the multi-bit output data word.

12. The circuit of claim 11 , wherein the DWA control circuit processes a previous cycle of the multi-bit output data word to generate the multi-bit selection signal for controlling the crossbar switch matrix to DWA convert a current cycle of the thermometer coded multi-bit input data word to output a current cycle of the multi-bit output data word.

13. The circuit of claim 12 , wherein the DWA control circuit is further configured to receive the thermometer coded multi-bit input data word, and wherein a change in the multi-bit selection signal between cycles is inhibited in response to bits of the thermometer coded multi-bit input data word having either an all logic 1 value or an all logic 0 value.

14. The circuit of claim 13 , wherein the DWA control circuit comprises a logic circuit including:
an OR gate configured to receive bits of the thermometer coded multi-bit input data words and generate a first control signal if all bits have a logic 0 value;
a NAND gate configured to receive bits of the thermometer coded multi-bit input data words and generate a second control signal if all bits have a logic 1 value;
an AND gate configured to receive the first and second control signals and generate a third control signal in response thereto, said third control signal configured to inhibit change in the multi-bit selection signal.

15. The circuit of claim 12 , wherein the DWA control circuit is configured to generate the multi-bit selection signal in a manner such that only one bit in the multi-bit selection signal is asserted in any cycle, while all other bits are deasserted at that cycle.

16. The circuit of claim 15 , wherein said crossbar switch matrix operates to selectively connect bits of the thermometer coded multi-bit input data word to bits of the multi-bit output data word in a sequence having a barrel shifted position specified by aid one bit in the multi-bit selection signal that is asserted.

17. The circuit of claim 16 , wherein said DWA control circuit comprises a combinatorial logic circuit configured to find a bit location for an ending logic transition of the bits of the multi-bit output data word in the previous cycle and wherein the multi-bit selection signal specifies a bit location for a beginning logic transition of the bits of the multi-bit output data word in the current cycle.

18. The circuit of claim 17 , wherein the barrel shifted position places the bit location for the beginning logic transition for the current cycle of the multi-bit output data word adjacent to the bit location for the ending logic transition for the previous cycle of the multi-bit output data word.

19. The circuit of claim 16 , further comprising a memory circuit configured to store an output of the combinatorial logic circuit as the multi-bit selection signal, wherein storing of said output is inhibited if bits of the thermometer coded multi-bit input data word have either an all logic 1 value or an all logic 0 value.

20. The circuit of claim 19 , wherein said memory comprises a plurality of flip flops equal in number to a number of bits in the multi-bit data o

Assignees

• St Microelectronics Int Nv

Inventors

• Bal Ankur
• Singh Rupesh

Classifications

• H03M1/0665 Primary

  using data dependent selection of the elements, e.g. data weighted averaging · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M3/468

  Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M7/165 Primary

  Conversion to or from thermometric code · CPC title