Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment

Patent metadata

Field	Value
Publication number	US-9747396-B1
Application number	US-201615339314-A
Country	US
Kind code	B1
Filing date	Oct 31, 2016
Priority date	Oct 31, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit.

First claim

What is claimed is:

1. A method comprising:
driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support, wherein the interface unit is an alter display unit operable to inspect and modify a plurality of registers, logic units, and memory in a plurality of cores of the circuit design through a pervasive infrastructure establishing communication between the alter display unit and the cores;
examining a state of the circuit design through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator; and
determining a next action to perform in the initialization sequence based on the state of the circuit design as determined through the interface unit.

2. The method of claim 1 , further comprising:
setting the breakpoint to trigger based on execution of an expected number of cycles by the circuit design in the hardware-accelerated simulator.

3. The method of claim 1 , further comprising:
setting the breakpoint to trigger based on an internal signal state of the circuit design in the hardware-accelerated simulator.

4. The method of claim 1 , further comprising:
pausing execution of the initialization sequence based on triggering of the breakpoint;
setting one or more subsequent breakpoints based on the state of the circuit design as determined through the interface unit; and
resuming execution of the initialization sequence.

5. The method of claim 1 , wherein a circuit design verification system executes one or more scripts to select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.

6. The method of claim 5 , wherein the breakpoint is set to trigger during execution of the initialization sequence on the circuit design.

7. A system comprising:
a hardware-accelerated simulator;
a processor in communication with the hardware-accelerated simulator; and
a memory, storing program code, which when executed on the processor, performs an operation of circuit design verification, the operation comprising:
driving a plurality of commands to an interface unit of a circuit design in the hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support, wherein the interface unit is an alter display unit operable to inspect and modify a plurality of registers, logic units, and memory in a plurality of cores of the circuit design through a pervasive infrastructure establishing communication between the alter display unit and the cores;
examining a state of the circuit design through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator; and
determining a next action to perform in the initialization sequence based on the state of the circuit design as determined through the interface unit.

8. The system of claim 7 , wherein the operation further comprises:
setting the breakpoint to trigger based on execution of an expected number of cycles by the circuit design in the hardware-accelerated simulator.

9. The system of claim 7 , wherein the operation further comprises:
setting the breakpoint to trigger based on an internal signal state of the circuit design in the hardware-accelerated simulator.

10. The system of claim 7 , wherein the operation further comprises:
pausing execution of the initialization sequence based on triggering of the breakpoint;
setting one or more subsequent breakpoints based on the state of the circuit design as determined through the interface unit; and
resuming execution of the initialization sequence.

11. The system of claim 7 , wherein the operation is executed by one or more scripts to select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.

12. The system of claim 11 , wherein the breakpoint is set to trigger during execution of the initialization sequence on the circuit design.

13. A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform:
driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support, wherein the interface unit is an alter display unit operable to inspect and modify a plurality of registers, logic units, and memory in a plurality of cores of the circuit design through a pervasive infrastructure establishing communication between the alter display unit and the cores;
examining a state of the circuit design through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator; and
determining a next action to perform in the initialization sequence based on the state of the circuit design as determined through the interface unit.

14. The computer program product of claim 13 , wherein the program instructions executable by the processor to cause the processor to perform:
setting the breakpoint to trigger based on execution of an expected number of cycles by the circuit design in the hardware-accelerated simulator.

15. The computer program product of claim 13 , wherein the program instructions executable by the processor to cause the processor to perform:
setting the breakpoint to trigger based on an internal signal state of the circuit design in the hardware-accelerated simulator.

16. The computer program product of claim 13 , wherein the program instructions executable by the processor to cause the processor to perform:
pausing execution of the initialization sequence based on triggering of the breakpoint;
setting one or more subsequent breakpoints based on the state of the circuit design as determined through the interface unit; and
resuming execution of the initialization sequence.

17. The computer program product of claim 13 , wherein the program instructions comprise one or more scripts to select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.

18. The computer program product of claim 17 , wherein the breakpoint is set to trigger during execution of the initialization sequence on the circuit design.

Assignees

• IBM

Inventors

• Chatterjee Debapriya
• Kapoor Shakti
• Schumann John A

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F11/3466

  Performance evaluation by tracing or monitoring · CPC title

• G01R31/318533 Primary

  using scanning techniques, e.g. LSSD, Boundary Scan, JTAG · CPC title