System and method for stopping integrated circuit simulation

Patent metadata

Field	Value
Publication number	US-9317636-B1
Application number	US-63737406-A
Country	US
Kind code	B1
Filing date	Dec 11, 2006
Priority date	Dec 11, 2006
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A system for simulating hardware is disclosed wherein stopping the simulating for investigating a state of the simulating is constrained to occur at points of simulation synchronization. A delta cycle may be inserted into a simulation to provide a point of simulation synchronization. The delta cycle may be inserted at the beginning of a simulation loop.

First claim

What is claimed is:

1. A method for debugging an electronic hardware design, the electronic hardware design comprising a plurality of simulated hardware modules configured to operate in parallel and having a simulated state, the method comprising:
receiving, during execution of a simulation of the simulated hardware modules, a plurality of simulation stop requests requesting stoppage of the simulation from a plurality of simulation stoppers associated with a plurality of debuggers for the simulated hardware modules, the simulation stop requests including a first simulation stop request corresponding to a first simulated hardware module and generated in response to hitting of a breakpoint during execution of the simulation, the simulation stop requests including a second simulated stop request corresponding to a second simulated hardware module and generated during execution of the simulation;
responsive to receiving the simulation stop requests including the first simulation stop request and the second simulation stop request, creating a plurality of active simulation stopper entries for the plurality of simulation stoppers in a list of active simulation stoppers;
reaching a synchronization point of the simulation that is subsequent to the simulation stop requests, the simulated state of the simulation hardware modules being synchronized at the synchronization point;
at the synchronization point of the simulation, stopping the simulation and repeatedly performing the following steps until the list of active simulation stoppers is empty:
executing a corresponding investigative agent for the corresponding active simulation stopper entry;
removing the corresponding active simulation stopper entry from the list of active simulation stoppers; and

continuing the simulation responsive to the list of active simulation stoppers being empty.

2. The method of claim 1 , wherein the simulated hardware modules are simulated processors.

3. The method of claim 1 , wherein the simulation stop requests are received by a central application software controlling starting and stopping of said simulation.

4. The method of claim 1 , wherein the simulation is a SystemC simulation.

5. The method of claim 1 , wherein the synchronization point is a delta cycle.

6. The method of claim 1 , wherein the synchronization point is a sc_wait function.

7. The method of claim 1 , wherein the simulation is a sequential simulation of the plurality of simulated hardware modules and the simulation is an instruction set simulation.

8. The method of claim 1 , wherein the synchronization point is at a beginning of a simulation cycle.

9. The method of claim 1 , wherein the steps performed at the synchronization point of the simulation comprise:
executing a first investigative agent for a first active simulation stopper entry from the list of active simulation stoppers;
removing the first active simulation stopper entry from the list of active simulation stoppers;
executing a second investigative agent for a second active simulation stopper entry from the list of active simulation stoppers; and
removing the second active simulation stopper entry from the list of active simulation stoppers.

10. The method of claim 1 , the simulation stop requests include a third simulation stop request corresponding to the second simulated hardware module and generated during execution of the simulation.

11. An article of manufacture comprising a non-transitory computer usable media comprising computer usable instructions that, responsive to execution on a computer processor, causes the computer processor to perform operations comprising:
receiving, during execution of a simulation of the simulated hardware modules, a plurality of simulation stop requests requesting stoppage of the simulation from a plurality of simulation stoppers associated with a plurality of debuggers for the simulated hardware modules, the simulation stop requests including a first simulation stop request corresponding to a first simulated hardware module and generated in response to hitting of a breakpoint during execution of the simulation, the simulation stop requests including a second simulated stop request corresponding to a second simulated hardware module and generated during execution of the simulation;
responsive to receiving the simulation stop requests including the first simulation stop request and the second simulation stop request, creating a plurality of active simulation stopper entries for the plurality of simulation stoppers in a list of active simulation stoppers;
reaching a synchronization point of the simulation that is subsequent to the simulation stop requests, the simulated state of the simulation hardware modules being synchronized at the synchronization point;
at the synchronization point of the simulation, stopping the simulation and repeatedly performing the following steps until the list of active simulation stoppers is empty:
executing a corresponding investigative agent for the corresponding active simulation stopper entry;
removing the corresponding active simulation stopper entry from the list of active simulation stoppers; and

continuing the simulation responsive to the list of active simulation stoppers being empty.

12. The article of manufacture of claim 11 , wherein the simulated hardware modules are simulated processors.

13. The article of manufacture of claim 11 , wherein the simulation stop requests are received by a central application software controlling starting and stopping of said simulation.

14. The article of manufacture of claim 11 , wherein the simulation is a SystemC simulation.

15. The article of manufacture of claim 11 , wherein the synchronization point is a delta cycle.

16. The article of manufacture of claim 11 , wherein the synchronization point is a sc_wait function.

17. The article of manufacture of claim 11 , wherein the simulation is a sequential simulation of the plurality of simulated hardware modules and the simulation is an instruction set simulation.

18. The article of manufacture of claim 11 , wherein the synchronization point is at a beginning of a simulation cycle.

19. The article of manufacture of claim 11 , wherein the steps performed at the synchronization point of the simulation comprise:
executing a first investigative agent for a first active simulation stopper entry from the list of active simulation stoppers;
removing the first active simulation stopper entry from the list of active simulation stoppers;
executing a second investigative agent for a second active simulation stopper entry from the list of active simulation stoppers; and
removing the second active simulation stopper entry from the list of active simulation stoppers.

20. The article of manufacture of claim 11 , wherein the simulation stop requests include a third simulation stop request corresponding to the second simulated hardware module and generated during execution of the simulation.

Assignees

• Petras Dietmar
• Vanspauwen Niels
• Synopsys Inc

Inventors

• Petras Dietmar
• Vanspauwen Niels

Classifications

• G06F11/261

  by simulating additional hardware, e.g. fault simulation · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F17/5022 Primary

  Physics · mapped topic