Cavity structures in integrated circuit package supports

Patent metadata

Field	Value
Publication number	US-11557489-B2
Application number	US-201816113109-A
Country	US
Kind code	B2
Filing date	Aug 27, 2018
Priority date	Aug 27, 2018
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

First claim

The invention claimed is:

1. An integrated circuit (IC) package support, comprising:
a cavity in a dielectric material, wherein the cavity has a bottom surface and sidewalls, wherein the sidewalls include a first peripheral material proximate to the bottom surface of the cavity, a second peripheral material on the first peripheral material, and the dielectric material on the second peripheral material, and wherein the second peripheral material is different than the first peripheral material; and
conductive contacts at the bottom surface of the cavity, wherein the conductive contacts include the first peripheral material.

2. The IC package support of claim 1 , wherein the first peripheral material includes copper.

3. The IC package support of claim 1 , wherein the second peripheral material includes nickel, tungsten or titanium.

4. The IC package support of claim 1 , wherein a thickness of the first peripheral material is between 0.2 microns and 1.5 microns.

5. The IC package support of claim 1 , wherein a thickness of the second peripheral material is between 5 microns and 15 microns.

6. The IC package support of claim 1 , wherein a depth of the cavity is between 50 microns and 150 microns.

7. The IC package support of claim 1 , further comprising:
conductive structures in electrical contact with the conductive contacts.

8. The IC package support of claim 1 , wherein a bottom surface of the first peripheral material is coplanar with a bottom surface of the conductive contacts.

9. The IC package support of claim 1 , wherein the IC package support is a package substrate or an interposer.

10. The IC package support of claim 1 , further comprising:
an IC component in the cavity, wherein conductive contacts of the IC component are coupled to the conductive contacts.

11. An integrated circuit (IC) package, comprising:
an IC package support, including:
a cavity having a bottom surface and sidewalls, the cavity including conductive contacts disposed at the bottom surface of the cavity, wherein the bottom surface of the cavity is a surface of a layer of dielectric material, and wherein the sidewalls include a peripheral material on the surface of the layer of dielectric material; and
an IC component in the cavity, wherein conductive contacts of the IC component are electrically coupled by solder to the conductive contacts at the bottom surface of the cavity.

12. The IC package of claim 11 , wherein the IC component is a packaged component.

13. The IC package of claim 11 , wherein the IC component is a multi-layer ceramic capacitor, a chip capacitor, or an inductor.

14. The IC package of claim 11 , wherein the IC package support further includes conductive contacts for first-level interconnects at a face of the IC package support, and the cavity is at the face.

15. The IC package of claim 11 , wherein the IC package support further includes conductive contacts for second-level interconnects at a face of the package support, and the cavity is at the face.

16. A computing device, comprising:
a circuit board; and
an integrated circuit (IC) package coupled to the circuit board, wherein the IC package includes:
an IC package support having a cavity with a bottom surface and sidewalls, the cavity including conductive contacts at the bottom surface of the cavity, and the sidewalls of the cavity including a peripheral material proximate to the bottom surface of the cavity, wherein the a peripheral material includes a metal and is insulated from power, ground, and signal pathways through the IC package support; and
an IC component electrically coupled to the conductive contacts at the bottom surface of the cavity.

17. The computing device of claim 16 , wherein the circuit board is a motherboard.

18. The computing device of claim 16 , wherein the computing device is a handheld computing device or a server computing device.

19. The computing device of claim 16 , wherein the IC package further includes one or more dies coupled to the face of the IC package support.

20. The computing device of claim 16 , further comprising:
a display device communicatively coupled to the circuit board or
wireless communication circuitry communicatively coupled to the circuit board.

Assignees

• Intel Corp

Inventors

• Jain Rahul
• Vadlamani Sai
• Zhao Junnan
• Park Ji Yong
• Lee Kyu Oh
• Xu Cheng

Classifications

• H01L24/08

  Electricity · mapped topic

• H01L2924/15153

  Electricity · mapped topic

• H01L24/06

  Electricity · mapped topic

• H01L2224/08235

  Electricity · mapped topic

• H01L2224/06181

  Electricity · mapped topic