Interposer substrate, semiconductor structure and fabricating process thereof

Patent metadata

Field	Value
Publication number	US-2016240481-A1
Application number	US-201514624331-A
Country	US
Kind code	A1
Filing date	Feb 17, 2015
Priority date	Feb 17, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.

First claim

1 . An interposer substrate, comprising:
a first core layer; a first conductive layer on a first side of the interposer substrate and comprising a plurality of first pads; a second conductive layer on a second side of the interposer substrate and comprising a plurality of second pads, wherein the second side of the interposer substrate is opposite the first side of the interposer substrate; a plurality of conductive vias electrically connecting the first conductive layer and the second conductive layer; and a reinforcement structure in the interposer substrate; wherein the interposer substrate defines a cavity.

2 . The interposer substrate according to claim 1 , wherein the reinforcement structure is a reinforcing layer formed inside the cavity and in contact with the first core layer.

3 . The interposer substrate according to claim 2 , wherein the reinforcing layer comprises a metal or a polymer.

4 . The interposer substrate according to claim 2 , wherein a thickness of the reinforcing layer is less than or equal to a depth of the cavity.

5 . The interposer substrate according to claim 1 , wherein the reinforcement structure is a ring formed around the cavity.

6 . The interposer substrate according to claim 5 , further comprising a first insulating layer on the first side of the interposer substrate.

7 . The interposer substrate according to claim 6 , wherein the ring is embedded in the first insulating layer.

8 . The interposer substrate according to claim 6 , further comprising a second insulating layer on the second side of the interposer substrate, wherein the ring is embedded in the second insulating layer.

9 . The interposer substrate according to claim 5 , wherein the ring is embedded in the first core layer.

10 . The interposer substrate according to claim 1 , wherein the reinforcement structure is a second core layer adjacent to the first core layer, wherein a ratio of the modulus of rigidity of the first core layer to the modulus of rigidity of the second core layer is less than one, and the second core layer and the cavity are on the same side of the interposer substrate.

11 . The interposer substrate according to claim 10 , wherein a thickness of the second conductive layer is substantially equal to a thickness of the second core layer.

12 . The interposer substrate according to claim 1 , further comprising a first insulating layer on the first side of the interposer substrate and a second insulating layer on the second side of the interposer substrate, wherein the first insulating layer defines a recess at a location corresponding to the cavity, wherein a size of the recess is not greater than a size of the cavity, and the recess and the cavity are on different sides of the interposer substrate.

13 . The cavity interposer substrate according to claim 12 , wherein the first core layer is partially exposed in the recess.

14 . The interposer substrate according to claim 1 , further comprising a first insulating layer on the first side of the interposer substrate and a second insulating layer on the second side of the interposer substrate, wherein the second insulating layer and the cavity are on the same side of the interposer substrate, and a ratio of a thickness of the first insulating layer to a thickness of the second insulating layer is less than one.

15 . The interposer substrate according to claim 1 , wherein the second conductive layer and the cavity are on the same side of the interposer substrate and a ratio of a thickness of the first conductive layer to a thickness of the second conductive layer is less than one.

16 . The interposer substrate according to claim 1 , wherein the second conductive layer and the cavity are on the same side of the interposer substrate, and the second conductive layer is embedded in the first core layer.

17 - 20 . (canceled)

21 . A semiconductor structure comprising:
a base substrate having a first surface including a plurality of base substrate pads thereon; an interposer substrate comprising:
a first core layer,
a first conductive layer on a first side of the interposer substrate and comprising a plurality of first pads,
a second conductive layer on a second side of the interposer substrate and comprising a plurality of second pads,
a plurality of conductive vias electrically connecting the first conductive layer and the second conductive layer, and
a reinforcement structure in the interposer substrate, wherein the interposer substrate defines a cavity; and
wherein at least one of the first and the second pads is electrically coupled to at least one of the plurality of base substrate pads; and
a semiconductor device positioned at least partially within the cavity between the base substrate and the interposer substrate.

22 . The semiconductor structure according to claim 21 , wherein the reinforcement structure is a reinforcing layer formed inside the cavity and in contact with the first core layer.

23 . The semiconductor structure according to claim 21 , wherein the reinforcement structure is a ring formed around the cavity.

24 . The semiconductor structure according to claim 21 , wherein the reinforcement structure is a second core layer adjacent to the first core layer, wherein a ratio of the modulus of rigidity of the first core layer to the modulus of rigidity of the second core layer is less than one, and the second core layer and the cavity are on the same side of the interposer substrate.

25 . A substrate, comprising:
a core layer, the core layer defining an accommodating cavity; a first conductive layer disposed on a first surface of the core layer; a second conductive layer embedded in the core layer and exposed at a second surface of the core layer; a conductive via electrically connecting the first conductive layer with the second conductive layer; a first insulating layer disposed over the core layer and the first conductive layer, the first insulating layer exposing portions of the first conductive layer; a second insulating layer disposed over the core layer and exposing portions of the second conductive layer; and a reinforcing structure configured to reduce warpage of the substrate.

26 . The substrate of claim 25 , wherein the reinforcing structure comprises a reinforcing layer disposed on the core layer within the cavity.

27 . The substrate of claim 25 , wherein the reinforcing structure comprises a ring structure.

28 . The substrate of claim 25 , wherein the core layer comprises a first core layer and a second core layer, the first core layer and the second core layer comprising different materials, and wherein the reinforcing structure comprises the second core layer.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen Chia-Ching
• Kao Chin-Li
• Chang Hung-Jen
• Chen Tang-Yuan
• Lai wei-hong

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title