Integrated circuit devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11552176-B2
Application number	US-202117329361-A
Country	US
Kind code	B2
Filing date	May 25, 2021
Priority date	May 25, 2020
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a fin-type active area that extends on a substrate in a first direction;
a gate structure that extends on the substrate in a second direction that intersects with the first direction, with the gate structure extending across the fin-type active area;
source/drain areas arranged on first and second sides of the gate structure; and
a contact structure electrically connected to the source/drain areas,
wherein the source/drain areas each comprise a plurality of merged source/drain structures, with each source/drain area comprising a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprising at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another,
wherein a level of each first point is closer to the substrate than each second point in a third direction perpendicular to an upper surface of the substrate, and
wherein a bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

2. The integrated circuit device of claim 1 , further comprising:
a silicide layer between the contact structure and the source/drain area at each first point, and
a residual barrier between the contact structure and the source/drain area at each second point.

3. The integrated circuit device of claim 2 , wherein a lowermost surface of the silicide layer is closer to the substrate than that of a lowermost surface of the residual barrier.

4. The integrated circuit device of claim 2 , wherein a length of the silicide layer in the second direction is greater than that of the residual barrier in the second direction.

5. The integrated circuit device of claim 2 , wherein the silicide layers and the residual barriers are alternately arranged in the second direction.

6. The integrated circuit device of claim 2 , wherein the contact structure comprises:
a barrier metal layer that extends onto the silicide layer and the residual barrier; and
a contact metal layer on the barrier metal layer.

7. The integrated circuit device of claim 6 , further comprising:
an etch stop layer arranged along the outside of the source/drain area, free from contact with the contact structure and in contact with the barrier metal layer.

8. The integrated circuit device of claim 1 , wherein the bottom surface of the contact structure comprises an undulation.

9. The integrated circuit device of claim 8 , wherein a phase of an upper surface of the source/drain area is the same as a phase of a lower surface of the contact structure.

10. The integrated circuit device of claim 1 , wherein the fin-type active area is aligned with one of the plurality of first points in the third direction.

11. An integrated circuit device comprising:
a plurality of fin-type active areas that protrude from a substrate;
a gate structure that crosses the plurality of fin-type active areas;
source/drain areas comprising merged source/drain structures arranged on first and second sides of the gate structure; and
a contact structure electrically connected to the merged source/drain structures,
wherein upper surfaces of each of the merged source/drain structures comprise an undulation, and
wherein silicide layers and residual barriers are alternately arranged along the undulation.

12. The integrated circuit device of claim 11 , wherein a number of fin-type active areas contacting the merged source/drain structures equals a number of silicide layers arranged on the merged source/drain structures.

13. The integrated circuit device of claim 12 , wherein a lower surface of the contact structure also comprises an undulation, and
wherein a lowest point of the lower surface of the contact structure is arranged above an upper portion of a fin-type active area of the plurality of fin-type active areas.

14. The integrated circuit device of claim 11 , wherein the contact structure comprises:
a contact metal layer arranged along upper surfaces of the silicide layer and the residual barrier; and
a barrier metal layer that conforms to an outside of the contact metal layer.

15. The integrated circuit device of claim 14 , wherein the residual barrier, the barrier metal layer, and the contact metal layer are sequentially arranged along a surface in which adjacent source/drain structures merge with each other in a vertical direction.

16. An integrated circuit device comprising:
a plurality of fin-type active areas that extend on a substrate in a first direction;
a gate structure that extends on the substrate in a second direction that intersects with the first direction, wherein the gate structure crosses the plurality of fin-type active areas;
source/drain areas arranged on first and second sides of the gate structure and on the plurality of fin-type active areas;
an interlayer insulating layer that covers the source/drain areas; and
a contact structure electrically connected to the source/drain areas through the interlayer insulating layer,
wherein the source/drain areas comprise a plurality of source/drain structures merged together,
wherein an upper surface of each source/drain area comprises a first point corresponding to a center of each of the source/drain structures and a second point corresponding to where adjacent source/drain structures are merged,
wherein each first point is closer to the substrate than each second point in a third direction perpendicular to an upper surface of the substrate,
wherein a silicide layer is arranged between the contact structure and each of the source/drain structures at each first point, and
wherein a residual barrier is arranged between the contact structure and each of the source/drain structures at each second point.

17. The integrated circuit device of claim 16 , wherein the contact structure comprises:
a contact metal layer arranged along upper surfaces of the silicide layer and the residual barrier; and
a barrier metal layer that conforms to an outside of the contact metal layer.

18. The integrated circuit device of claim 17 , wherein the barrier metal layer comprises titanium (Ti), and wherein the contact metal layer comprises tungsten (W).

19. The integrated circuit device of claim 18 , wherein the silicide layer comprises a combination of a material forming the barrier metal layer and a material forming the source/drain structure.

20. The integrated circuit device of claim 16 , wherein the residual barrier comprises silicon nitride or silicon oxynitride.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sanghyun
• Kang Sungwoo
• Park Jongchul
• Oh Youngmook
• Lee Jeongyun

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title