Logic buffer circuit and method

Patent metadata

Field	Value
Publication number	US-11545977-B2
Application number	US-202117227815-A
Country	US
Kind code	B2
Filing date	Apr 12, 2021
Priority date	May 3, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit includes a first transistor and an RC network including a resistor and a capacitor, the first transistor is coupled in series with the resistor between a power supply node and a reference node, and the buffer and the RC circuit are configured to generate an output signal based on the input signal.

First claim

What is claimed is:

1. A buffer circuit comprising:
an input terminal configured to receive an input signal;
an output terminal;
a buffer; and
a resistor-capacitor (RC) circuit coupled in series with the buffer between the input terminal and the output terminal,
wherein
the RC circuit comprises a first transistor and an RC network comprising a resistor and a capacitor,
the first transistor is coupled in series with the resistor between a power supply node and a reference node, and
the buffer and the RC circuit are configured to generate an output signal based on the input signal.

2. The buffer circuit of claim 1 , wherein the RC network comprises the capacitor arranged in parallel with the resistor.

3. The buffer circuit of claim 1 , wherein the RC network comprises the capacitor coupled in series with the resistor between the power supply node and the reference node.

4. The buffer circuit of claim 1 , wherein the RC circuit comprises:
an RC circuit output terminal coupled to the first transistor and an input terminal of the buffer; and
a second transistor coupled between the output terminal of the RC circuit and the resistor, wherein
the first transistor is a first one of an NMOS or PMOS transistor,
the second transistor is a second one of the NMOS or PMOS transistor, and
each of a gate of the first transistor and a gate of the second transistor is coupled to an input terminal of the RC circuit.

5. The buffer circuit of claim 1 , wherein
each of the buffer and the RC circuit comprises an inverter, and
the buffer and the RC circuit are configured to generate the output signal having a same low or high logical voltage level as that of the input signal in a steady state.

6. The buffer circuit of claim 1 , wherein the buffer and the RC circuit are configured to generate the output signal having an increased transition time between logical voltage levels relative to a transition time between logical voltage levels of the input signal by a time ranging from 0.2 microseconds (μs) to 1000 μs.

7. The buffer circuit of claim 1 , wherein
the buffer is a first inverter of a plurality of inverters coupled between the input and output terminals,
the first inverter of the plurality of inverters is coupled between the RC circuit and the output terminal, and
a second inverter of the plurality of inverters is coupled to the input terminal and comprises a hysteresis circuit.

8. The buffer circuit of claim 1 , further comprising:
a first logic circuit arranged in parallel with the series arrangement of the buffer and RC circuit; and
a second logic circuit coupled between the first logic circuit and the output terminal,
wherein the buffer circuit is configured to generate the output signal further based on the first and second logic circuits.

9. A system comprising:
an overvoltage protection circuit configured to generate a protected signal at an overvoltage protection circuit output terminal; and
a buffer circuit configured to generate a buffer circuit output signal at a buffer circuit output terminal, the buffer circuit comprising:
an input terminal coupled to the overvoltage protection circuit output terminal;
a buffer; and
a resistor-capacitor (RC) circuit coupled in series with the buffer between the input terminal and the buffer circuit output terminal,
wherein
the buffer circuit and the RC circuit are configured to generate the buffer circuit output signal based on the protected signal,
the RC circuit comprises a first transistor and an RC network comprising a resistor and a capacitor, and
the first transistor is coupled in series with the resistor between a power supply node and a reference node.

10. The system of claim 9 , wherein the RC network comprises the capacitor arranged in parallel with the resistor.

11. The system of claim 9 , wherein the RC network comprises the capacitor coupled in series with the resistor between the power supply node and the reference node.

12. The system of claim 9 , further comprising a power-on circuit configured to receive the buffer circuit output signal.

13. The system of claim 9 , wherein the buffer circuit comprises a first logic circuit configured to generate the buffer circuit output signal based on the protected signal received at the RC circuit and at a second logic circuit.

14. The system of claim 9 , wherein the overvoltage protection circuit is configured to generate the protected signal having a voltage level at or near a reference voltage level for a duration ranging from 0.1 microseconds (μs) to 100 μs.

15. A method of operating a buffer circuit, the method comprising:
receiving a logic signal at an input terminal of the buffer circuit;
sequentially inverting the logic signal using each of a resistor-capacitor (RC) circuit and a buffer, the RC circuit being coupled to an input terminal of the buffer and comprising a transistor and an RC network comprising a resistor and a capacitor; and
outputting the sequentially inverted logic signal at an output terminal of the buffer circuit,
wherein the inverting the logic signal using the RC circuit comprises:
using the resistor to couple the input terminal of the buffer to one of a power supply voltage node or a reference voltage node; and
using the transistor to decouple the input terminal of the buffer from the other of the power supply voltage node or the reference voltage node.

16. The method of claim 15 , further comprising outputting the logic signal from an overvoltage protection circuit.

17. The method of claim 15 , wherein the receiving the logic signal at the input terminal of the buffer circuit comprises receiving the logic signal at an input pad of an integrated circuit (IC) chip.

18. The method of claim 15 , wherein the outputting the sequentially inverted logic signal at the output terminal of the buffer circuit comprises outputting a reset signal of a power-on circuit of an integrated circuit (IC) chip.

19. The method of claim 15 , wherein the inverting the logic signal using the RC network comprises coupling and decoupling the input terminal of the buffer including a hysteresis circuit.

20. The method of claim 15 , wherein the using the transistor to decouple the input terminal of the buffer from the other of the power supply voltage node or the reference voltage node comprises using an NMOS transistor to decouple the input terminal of the buffer from the reference voltage node.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Wan-Yen
• Chan Yuan-Ju
• Chen Bo-Ting

Classifications

• H03K19/00323

  Delay compensation · CPC title

• H03K17/08 Primary

  Modifications for protecting switching circuit against overcurrent or overvoltage · CPC title

• H03K19/00384 Primary

  in field effect transistor circuits · CPC title

• H03K19/0185

  using field effect transistors only · CPC title

• H03K19/09443

  using a combination of enhancement and depletion transistors · CPC title