Charge pumps, logic circuits including charge pumps, logic devices including logic circuits, and methods of operating logic circuits
US-12323143-B2 · Jun 3, 2025 · US
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using a combination of enhancement and depletion transistors
using a combination of enhancement and depletion transistors · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H03K19/09443 |
| Official title | {using a combination of enhancement and depletion transistors} |
| Display label | using a combination of enhancement and depletion transistors |
| Total patents | 14 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 1 |
| 2016 | 3 |
| 2017 | 1 |
| 2018 | 1 |
| 2020 | 2 |
| 2021 | 2 |
| 2022 | 1 |
| 2023 | 1 |
| 2024 | 1 |
| 2025 | 1 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Charge pumps, logic circuits including charge pumps, logic devices including logic circuits, and methods of operating logic circuits
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