Logic buffer circuit and method

Patent metadata

Field	Value
Publication number	US-10979049-B2
Application number	US-202016789072-A
Country	US
Kind code	B2
Filing date	Feb 12, 2020
Priority date	May 3, 2019
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A buffer circuit includes an input terminal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit is configured to increase a transition time between logical voltage levels of an output signal generated at the output terminal relative to a transition time between logical voltage levels of an input signal received at the input terminal, and the transition time of the output signal is based on a duration of a logic inversion of the input signal.

First claim

What is claimed is:

1. A buffer circuit comprising:
an input terminal;
an output terminal;
a buffer; and
a resistor-capacitor (RC) circuit coupled in series with the buffer between the input terminal and the output terminal,
wherein
the RC circuit is configured to increase a transition time between logical voltage levels of an output signal generated at the output terminal relative to a transition time between logical voltage levels of an input signal received at the input terminal, wherein:
the RC circuit comprises a first transistor and an RC network, wherein the first transistor is coupled in series with the RC network between a power supply node and a reference node;
the RC network comprises a resistor and a capacitor, wherein the resistor is in parallel with the capacitor; and
the output signal transition time is based on a duration of a logic inversion of the input signal.

2. The buffer circuit of claim 1 , wherein the first transistor is an NMOS transistor.

3. The buffer circuit of claim 1 , wherein
the RC circuit further comprises a second transistor coupled in series between the first transistor and the RC network,
the first and second transistors are different transistor types,
a gate of each of the first and second transistors is coupled to an input terminal of the RC circuit, and
a drain of each of the first and second transistors is coupled to an output terminal of the RC circuit.

4. The buffer circuit of claim 1 , wherein the RC circuit comprises:
an output node coupled to the first transistor, the RC network, and the buffer.

5. The buffer circuit of claim 1 , wherein the buffer comprises a hysteresis circuit.

6. The buffer circuit of claim 1 , wherein the buffer comprises an inverter.

7. The buffer circuit of claim 1 , wherein the RC circuit is coupled between the buffer and the input terminal.

8. The buffer circuit of claim 7 wherein
the buffer is one buffer of a plurality of buffers, and
the RC circuit is coupled between an entirety of the plurality of buffers and the input terminal.

9. The buffer circuit of claim 1 , wherein the first transistor is configured to decouple the input terminal of the buffer from one of either the power supply node or the reference node.

10. A system comprising:
an overvoltage protection circuit configured to generate a protected signal at an overvoltage protection circuit output terminal; and
a buffer circuit configured to generate a buffer circuit output signal at a buffer circuit output terminal, the buffer circuit comprising:
an input terminal coupled to the overvoltage protection circuit output terminal;
a buffer;
a resistor-capacitor (RC) circuit coupled in series with the buffer between the input terminal and the buffer circuit output terminal,

wherein the RC circuit is configured to increase a transition time between logical voltage levels of the buffer circuit output signal relative to a transition time between logical voltage levels of the protected signal and wherein:
the RC circuit comprises a first transistor and an RC network, wherein the first transistor is coupled in series with the RC network between a power supply node and a reference node; and
the RC network comprises a resistor and a capacitor, wherein the resistor is in parallel with the capacitor.

11. The system of claim 10 , wherein
the buffer circuit is part of an integrated circuit (IC) chip separate from the overvoltage protection circuit, and
the input terminal of the buffer circuit comprises a contact pad of the IC chip.

12. The system of claim 10 , wherein the overvoltage protection circuit comprises a switching device configured to generate the protected signal by coupling the overvoltage protection circuit output terminal to the reference node responsive to a detected voltage level.

13. The system of claim 10 , wherein the RC circuit is configured to increase the transition time of the buffer circuit output signal based on a threshold voltage of the buffer.

14. The system of claim 13 , wherein
the overvoltage protection circuit is configured to couple the overvoltage protection circuit output terminal to the reference node for a duration based on an electrostatic discharge (ESD) model, and
the RC circuit is configured to increase the transition time of the buffer circuit output signal further based on the duration.

15. The system of claim 10 , wherein the buffer circuit is a component of a system on a chip (SoC) configured to perform a reset operation responsive to the buffer circuit output signal.

16. The system of claim 10 , wherein:
the first transistor is an NMOS transistor comprising a gate coupled to the input terminal of the buffer circuit, a source terminal coupled to the reference node, and a drain terminal coupled to an input terminal of the buffer; and
the RC network is coupled between the drain terminal of the NMOS transistor and the power supply node.

17. The system of claim 16 , wherein the RC circuit further comprises a PMOS transistor comprising a gate coupled to the input terminal of the buffer circuit, a drain terminal coupled to the drain terminal of the NMOS transistor, and a source terminal coupled to the RC network.

18. A method of operating a buffer circuit, the method comprising:
receiving a logic signal at an input terminal of the buffer circuit;
sequentially inverting the logic signal using each of a resistor-capacitor (RC) circuit and a buffer, the RC circuit being coupled to an input terminal of the buffer, wherein:
the RC circuit comprises a first transistor and an RC network, wherein the first transistor is coupled in series with the RC network between a power supply voltage node and a reference voltage node; and
the RC network comprises a resistor and a capacitor, wherein the resistor is in parallel with the capacitor; and

outputting the sequentially inverted logic signal at an output terminal of the buffer circuit,
wherein the inverting the logic signal using the RC circuit comprises using the RC network to couple the input terminal of the buffer to one of the power supply voltage node or the reference voltage node.

19. The method of claim 18 , wherein the using the RC network to couple the input terminal of the buffer to the one of the power supply voltage node or the reference voltage node comprises using the first transistor to decouple the input terminal of the buffer from the other of the power supply voltage node or the reference voltage node.

20. The method of claim 18 , wherein
the receiving the logic signal at the input terminal of the buffer circuit comprises receiving the logic signal at an input pad of a system on a chip (SoC), and
the outputting the sequentially inverted logic signal comprises outputting a reset signal of the SoC.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Wan-Yen
• Chan Yuan-Ju
• Chen Bo-Ting

Classifications

• H03K19/09443

  using a combination of enhancement and depletion transistors · CPC title

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title

• H03K19/0185

  using field effect transistors only · CPC title

• H03K17/08 Primary

  Modifications for protecting switching circuit against overcurrent or overvoltage · CPC title

• H03K19/00384 Primary

  in field effect transistor circuits · CPC title