Shared ESD circuitry

Patent metadata

Field	Value
Publication number	US-9553446-B2
Application number	US-201414529282-A
Country	US
Kind code	B2
Filing date	Oct 31, 2014
Priority date	Oct 31, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

An integrated circuit including ESD circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an ESD event on any of the terminal segments. The shared ESD circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from ESD events on each segment. The shared ESD circuitry includes a trigger circuit that is coupled to nodes coupled to terminals of each segment to detect an ESD event on each segment.

First claim

What is claimed is:

1. An integrated circuit comprising:
an ESD clamp circuit;
a first bus coupled to a first current electrode of the ESD clamp circuit;
a first diode coupled between the first bus and the first current electrode;
a second bus coupled to the first current electrode of the ESD clamp circuit;
a second diode coupled between the second bus and the first current electrode;
a first plurality of terminals, each terminal of the first plurality coupled to the first bus;
a second plurality of terminals, each terminal of the second plurality coupled to the second bus; and
a trigger circuit including a first input coupled to a first node to sense an ESD event occurring on at least one terminal of the first plurality of terminals, a second input coupled to a second node to sense an ESD event occurring on at least one terminal of the second plurality of terminals, and an output coupled to a control electrode of the ESD clamp circuit for making the ESD clamp circuit conductive in response to a sensed ESD event on at least one terminal of the first plurality of terminals to discharge current from the sensed ESD event on the first bus through the first diode and for making the ESD clamp circuit conductive in response to a sensed ESD event on at least one terminal of the second plurality of terminals to discharge current from the sensed ESD event on the second bus through the second diode.

2. The integrated circuit of claim 1 , wherein the first node is a node of the first bus and the second node is a node of the second bus.

3. The integrated circuit of claim 1 , wherein:
the first node is a node of a third bus that is a separate bus from the first bus, each terminal of the first plurality of terminals is coupled to the third bus; and
the second node is a node of a fourth bus that is a separate bus from the second bus, each terminal of the second plurality of terminals is coupled to the fourth bus.

4. The integrated circuit of claim 1 , further comprising:
a first plurality of ESD clamp circuits coupled to the first bus for discharging current on the first bus from an ESD event, wherein the first plurality of ESD clamp circuits is not coupled to the second bus to discharge current on the second bus from an ESD event; and
a second plurality of ESD clamp circuits coupled to the second bus for discharging current on the second bus from an ESD event, wherein the second plurality of ESD clamp circuits is not coupled to the first bus to discharge current on the first bus from an ESD event.

5. The integrated circuit of claim 4 , further comprising:
a second trigger circuit including a first input coupled to the first node and an output coupled to a control electrode of each of the first plurality of ESD clamp circuits;
a third trigger circuit including a first input coupled to the second node and an output coupled to a control electrode of each of the second plurality of ESD clamp circuits.

6. The integrated circuit of claim 1 , wherein the trigger circuit further includes:
a first circuit portion, the first circuit portion including the first input and a first portion output coupled to the output of the trigger circuit, the first portion output for providing an indication of an ESD event occurring on at least one terminal of the first plurality of terminals;
a second circuit portion, the second circuit portion including the second input and a second portion output coupled to the output of the trigger circuit, the second portion output for providing an indication of an ESD event occurring on at least one terminal of the second plurality of terminals.

7. The integrated circuit of claim 6 , wherein the first portion output and the second portion output are coupled in a wired-OR configuration.

8. The integrated circuit of claim 6 , wherein the first node supplies power to the first circuit portion when an ESD event is occurring on at least one terminal of the first plurality of terminals and the second node supplies power to the second circuit portion when an ESD event is occurring on at least one terminal of the second plurality of terminals.

9. The integrated circuit of claim 1 , wherein the ESD clamp circuit is characterized as a termination clamp circuit for the first plurality of terminals and the second plurality of terminals.

10. The integrated circuit of claim 1 , wherein the trigger circuit comprises a first R-C circuit coupled to the first input to detect an ESD event occurring on at least one terminal of the first plurality of terminals and comprises a second R-C circuit coupled to the second input to detect an ESD event occurring on at least one terminal of the second plurality of terminals.

11. The integrated circuit of claim 1 , wherein the first plurality of terminals is located in a first region of the integrated circuit and the second plurality of terminals is located in a second region of the integrated circuit, wherein the ESD clamp circuit is located between the first region and the second region.

12. The integrated circuit of claim 11 , wherein the first and second regions are located proximate to an edge of the integrated circuit.

13. An integrated circuit comprising:
a first bus;
a second bus;
a first ESD clamp circuit coupled to the first bus for discharging current on the first bus from an ESD event, wherein the first ESD clamp circuit is not coupled to the second bus to discharge current on the second bus from an ESD event;
a second ESD clamp circuit coupled to the second bus for discharging current on the second bus from an ESD event, wherein the second ESD clamp circuit is not coupled to the first bus to discharge current on the first bus from an ESD event; and
a third ESD clamp circuit coupled to the first bus for discharging current on the first bus from an ESD event and to the second bus for discharging current on the second bus from an ESD event.

14. The integrated circuit of claim 13 , further comprising:
a first trigger circuit including a first input coupled to a first node and an output coupled to a control electrode of the first ESD clamp circuit for making the first ESD clamp circuit conductive in response to a detected ESD event to discharge current on the first bus from the detected ESD event;
a second trigger circuit including a first input coupled to a second node and an output coupled to a control electrode of the second ESD clamp circuit for making the second ESD clamp circuit conductive in response to a detected ESD event to discharge current on the second bus from the detected ESD event; and
a third trigger circuit including a first input coupled to the first node and a second input coupled to the second node, and an output coupled to a control electrode of the third ESD clamp circuit for making the third ESD clamp circuit conductive in response to a detected ESD event to discharge current from at least one of a group comprising the first bus and the second bus from the detected ESD event.

15. The integrated circuit of claim 13 further comprising:
core circuitry;
a first plurality of I/O terminals coupled to the first bus and coupled to the core circuitry;
a second plurality of I/O terminals coupled to the second bus and coupled to the core circuitry.

16. The integrated circuit of claim 13 , wherein the first bus is characterized as a power bus and the second bus is characterized as a power bus.

17. The integrated circuit of claim 13 , wherein the third ESD clamp circuit is at least twice a size in area of each of the first ESD clamp circuit and the second ESD clamp circuit.

18. An integrat

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Gerdemann Alex P
• Etherton Melanie
• Miller James W
• Moosa Mohamed S
• Ruth Robert S
• Stockinger Michael A

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title