High-voltage devices integrated on semiconductor-on-insulator substrate

Patent metadata

Field	Value
Publication number	US-11545570-B2
Application number	US-202016736818-A
Country	US
Kind code	B2
Filing date	Jan 8, 2020
Priority date	Jan 8, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor-on-insulator (SOI) substrate comprising a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate;
a source region and a drain region disposed directly on the bulk substrate;
a drift well in the bulk substrate;
an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the drift well of the bulk substrate; and
a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.

2. The device of claim 1 , further comprising a body well in the bulk substrate, the body well is adjacent to the drift well.

3. The device of claim 1 , wherein the isolation structure has a top surface that is coplanar with a top surface of the semiconductor layer.

4. The device of claim 1 , wherein the isolation structure has a top surface that is completely covered by the gate structure.

5. The device of claim 1 , wherein the gate structure comprises a gate electrode disposed on a gate stack, the gate stack being disposed on the semiconductor layer.

6. The device of claim 1 , wherein the gate structure and the semiconductor layer are of the same material.

7. The device of claim 2 , wherein the body well is spaced apart from the drift well by a gap spacing.

8. The device of claim 2 , wherein the body well adjoins the drift well.

9. The device of claim 2 , wherein the drift well and the drain region are of the same conductivity type.

10. The device of claim 2 , wherein the drift well and the body well have opposite conductivity types with respect to each other.

11. The device of claim 2 , further comprising a drain extension region in the drift well, the drain extension region being located between the drain region and the gate structure.

12. The device of claim 11 , wherein the insulating layer and the semiconductor layer extend laterally to cover the drain extension region.

13. A method of forming a semiconductor device upon a semiconductor-on-insulator (SOI) substrate including a semiconductor layer, a bulk substrate, and an insulating layer disposed between the semiconductor layer and the bulk substrate, the method comprising:
patterning the insulating layer and the semiconductor layer to expose the bulk substrate and retain portions of the insulating layer and the semiconductor layer above the bulk substrate;
forming a drift well in the bulk substrate;
forming an isolation structure extending through the retained portions of the insulating layer and the semiconductor layer and terminating in the drift well of the bulk substrate;
forming a gate structure on the retained portion of the semiconductor layer; and
forming a source region and a drain region directly on the exposed bulk substrate, the gate structure being formed between the source region and the drain region.

14. The method of claim 13 , wherein the patterning of the insulating layer and the semiconductor layer includes removing portions of the insulating layer and the semiconductor layer to form openings that expose the bulk substrate.

15. The device of claim 8 , wherein the body well has an edge and the drift well has an edge, the edge of the body well adjoins the edge of the drift well at a location below the gate structure.

16. The device of claim 2 , wherein the gate structure partially overlaps with the drift well and the body well.

17. The device of claim 6 , wherein the gate structure has an epitaxial body, and the epitaxial body is of the same material as the semiconductor layer.

18. The device of claim 2 , further comprising a body region disposed on the body well.

19. The device of claim 18 , further comprising a second isolation structure in the bulk substrate, wherein the source region and the body region are separated by the second isolation structure.

20. The device of claim 2 , wherein the drain region is disposed on a top surface of the drift well.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Li Pinghui
• Linewih Handoko
• Chan Darin Arthur
• Jain Ruchil Kumar

Classifications

• H01L29/7824 Primary

  Electricity · mapped topic

• H01L29/66681

  Electricity · mapped topic

• H10D30/0281

  of lateral DMOS [LDMOS] FETs · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title