LDMOS transistor structures and integrated circuits including LDMOS transistor structures

Patent metadata

Field	Value
Publication number	US-10211336-B2
Application number	US-201715784422-A
Country	US
Kind code	B2
Filing date	Oct 16, 2017
Priority date	Jun 14, 2016
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

LDMOS transistor structures and integrated circuits including LDMOS transistor structures are provided. An exemplary integrated circuit including an LDMOS transistor structure includes a substrate including a first region and a second region. The substrate includes a bulk layer and, in the second region, an insulator layer overlying the bulk layer and a semiconductor layer overlying the insulator layer. The integrated circuit further includes a gate structure overlying the semiconductor layer. A channel region is formed in the semiconductor layer under the gate structure. The integrated circuit also includes a well contact region on the bulk layer in the first region, a source region overlying the substrate, and a drain region overlying the substrate. A drift region is located between the drain region and the gate structure.

First claim

What is claimed is:

1. An integrated circuit including an LDMOS transistor structure comprising:
a substrate including a first region and a second region, wherein the substrate includes a bulk layer and, in the second region, an insulator layer overlying the bulk layer and a semiconductor layer overlying the insulator layer;
a gate structure overlying the semiconductor layer, wherein a channel region is formed in the semiconductor layer under the gate structure;
a well contact region on the bulk layer in the first region, wherein the insulator layer is not located between the well contact region and the bulk layer;
a source region overlying the substrate; and
a drain region overlying the substrate, wherein a drift region is located between the drain region and the gate structure.

2. The integrated circuit of claim 1 wherein the drain region is formed in the semiconductor layer overlying the insulator layer.

3. The integrated circuit of claim 1 wherein the substrate includes a third region, wherein the drift region is located on the bulk layer in the third region, and wherein the drain region is located on the drift region.

4. The integrated circuit of claim 1 further comprising a well region in contact with the well contact region in the first region and with the insulator layer in the second region.

5. The integrated circuit of claim 1 further comprising an alignment gate overlying the drift region in the substrate.

6. The integrated circuit of claim 5 wherein the drain region is self-aligned with the alignment gate.

7. The integrated circuit of claim 6 wherein the drift region is located between the drain region and the gate structure.

8. The integrated circuit of claim 6 further comprising contacts to the gate structure and the drain region.

9. The integrated circuit of claim 1 further comprising contacts to the gate structure, the source region, and the drain region.

10. The integrated circuit of claim 1 further comprising:
isolation regions in the substrate, wherein the isolation regions separate a LDMOS device region from the well contact region; and
a contact to the bulk layer in the well contact well tap region.

11. The integrated circuit of claim 1 further comprising:
isolation regions in the substrate, wherein the isolation regions separate a LDMOS device region from the well contact region;
an epitaxial contact region over the bulk layer in the well contact region, wherein the drain region is an epitaxial drain region; and
contacts to the epitaxial contact region, the epitaxial drain region and the gate structure.

12. The integrated circuit of claim 1 further comprising an epitaxial contact region directly on a portion of the bulk layer.

13. An LDMOS transistor structure comprising:
a substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer, wherein the insulator layer is located at a first depth;
isolation regions in the substrate, wherein the isolation regions separate a LDMOS device region from a well tap region, and wherein the isolation regions extend from the semiconductor layer and past the insulator layer to a second depth deeper than the first depth;
a gate structure overlying the semiconductor layer in the LDMOS device region, wherein a channel region is formed in the semiconductor layer under the gate structure.

14. The LDMOS transistor structure of claim 13 further comprising contacts to the bulk layer in the well tap region and to the gate structure.

15. The LDMOS transistor structure of claim 13 further comprising:
an epitaxial contact region over the bulk layer in the well tap region;
an epitaxial drain region; and
contacts to the epitaxial contact region and to the gate structure.

16. The LDMOS transistor structure of claim 13 further comprising:
a source region overlying the substrate; and
a drain region overlying the substrate, wherein a drift region is located between the drain region and the gate structure;
contacts to the bulk layer in the well tap region, to the gate structure, to the source region, and to the drain region.

17. An LDMOS transistor structure comprising:
a substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer, wherein a portion of the bulk layer is not covered by the insulator layer and semiconductor layer; and
an epitaxial contact region directly on the portion of the bulk layer.

18. The LDMOS transistor structure of claim 17 further comprising:
a gate structure overlying the substrate, wherein a channel region is formed in the semiconductor layer under the gate structure;
a drain region on the epitaxial drift region, wherein the epitaxial drift region is located between the drain region and the gate structure; and
a source region overlying the substrate.

19. The LDMOS transistor structure of claim 18 further comprising contacts to the gate structure, the source region, and the drain region.

20. The LDMOS transistor structure of claim 17 further comprising an isolation region extending from the semiconductor layer and past the insulator layer into the bulk layer, wherein the isolation region isolates the portion of the bulk layer not covered by the insulator layer and semiconductor layer from the insulator layer and semiconductor layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Zhu Ming
• Lim Shi Ya Phyllis
• Li Pinghui
• Nga Yiang Aun

Classifications

• H01L29/1087

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/66689

  Electricity · mapped topic

• H01L29/0869

  Electricity · mapped topic

• H01L29/66507

  Electricity · mapped topic