Process for producing, from an SOI and in particular an FDSOI type substrate, transistors having gate oxides of different thicknesses, and corresponding integrated circuit

Patent metadata

Field	Value
Publication number	US-9786755-B2
Application number	US-201514930150-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Mar 18, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a substrate of the silicon-on-insulator type comprising a semiconductor film on a buried insulating layer on a carrier substrate;
a first zone of said substrate bounded on opposite sides by a first trench isolation and a second trench isolation;
a second zone of said carrier substrate bounded on opposite sides by a third trench isolation and a fourth trench isolation and including a portion of said buried insulating layer but wherein no portion of said semiconductor film of said substrate is present in the second zone between the third trench isolation and the fourth trench isolation;
a first transistor in said second zone comprising a first gate-dielectric region resting directly on the carrier substrate and formed by said portion of said buried insulating layer, wherein said buried insulating layer is not present in the second zone between a first edge of said portion forming said first gate-dielectric region and an edge of the third trench isolation and wherein said buried insulating layer is not present in the second zone between a second edge of said portion forming said first gate-dielectric region and an edge of the fourth trench isolation and without any presence of the semiconductor film on the first gate-dielectric region.

2. The integrated circuit according to claim 1 , further comprising a second transistor in said first zone comprising a second gate-dielectric region resting on said semiconductor film, said second gate-dielectric region being thinner than the first gate-dielectric region.

3. The integrated circuit according to claim 2 , wherein the second gate-dielectric region is formed by at least one layer of a first dielectric material and wherein the first transistor further comprises said at least one layer of the first dielectric located on said portion of the buried insulating layer.

4. The integrated circuit according to claim 1 , wherein a thickness of said portion of the buried insulating layer in the second zone is thinner than a thickness of the buried insulating layer of the silicon-on-insulator type substrate in the first zone.

5. The integrated circuit according to claim 1 , wherein said first transistor located in said second zone is a double-gate transistor comprising:
a floating-gate first region separated from the carrier substrate by said portion of said buried insulating layer; and
a control-gate second region separated from the floating-gate first region by a gate-dielectric region.

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Golanski Dominique
• Bidal Gregory
• Jeannot Simon

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H01L27/1207

  Electricity · mapped topic

• H01L27/12

  Electricity · mapped topic

• H01L29/7838

  Electricity · mapped topic