Co-fabricated bulk devices and semiconductor-on-insulator devices

Patent metadata

Field	Value
Publication number	US-9691787-B2
Application number	US-201514878332-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Oct 8, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

Bulk semiconductor devices are co-fabricated on a bulk semiconductor substrate with SOI devices. The SOI initially covers the entire substrate and is then removed from the bulk device region. The bulk device region has a thicker dielectric on the substrate than the SOI region. The regions are separated by isolation material, and may or may not be co-planar.

First claim

The invention claimed is:

1. A semiconductor structure, comprising:
a bulk semiconductor substrate;
at least one first dielectric layer over a first portion of the substrate;
a semiconductor layer over the first dielectric layer, creating a semiconductor-on-insulator (SOI) region;
at least one second dielectric layer over a second portion of the substrate, creating a bulk semiconductor device region horizontally adjacent the SOI region, wherein the at least one second dielectric layer is thicker than the at least one first dielectric layer; and
at least one layer of isolation material physically separating the SOI region from the bulk semiconductor device region down to the bulk semiconductor substrate;
wherein the bulk region further comprises a layer of semiconductor material above the second portion of the substrate under the at least one second dielectric layer, and wherein the SOI region and the bulk region are co-planar.

2. The semiconductor structure of claim 1 , wherein the layer of semiconductor material in the bulk region comprises epitaxial semiconductor material.

3. The semiconductor structure of claim 1 , further comprising:
at least one first type of semiconductor device in the SOI region; and
at least one second type of semiconductor device in the bulk semiconductor device region;
wherein the at least one second type of semiconductor device comprises at least one laterally diffused metal oxide semiconductor (LDMOS) detector.

4. The semiconductor structure of claim 1 , further comprising:
at least one first type of semiconductor device in the SOI region; and
at least one second type of semiconductor device in the bulk semiconductor device region;
wherein the at least one second type of semiconductor device comprises at least one transistor, the at least one transistor comprising work-function material in a gate structure.

5. The semiconductor structure of claim 1 , further comprising a sacrificial capping layer over the at least one second dielectric layer.

6. The semiconductor structure of claim 5 , wherein the sacrificial capping layer comprises titanium nitride.

7. A method, comprising:
providing a starting semiconductor structure, the structure comprising a bulk semiconductor substrate with a blanket dielectric layer thereover and a blanket layer of semiconductor material over the dielectric layer;
removing a common portion of both blanket layers, exposing an area of the substrate;
forming a layer of dielectric material over the area of the substrate;
removing at least one portion of the structure adjacent the area of the substrate with the layer of dielectric material thereover;
forming at least one layer of isolation material in one or more openings formed by the removing, the at least one layer of isolation material being co-planar with a top surface of the remaining blanket layer of semiconductor material; and
forming a top blanket layer of dielectric material over the structure, resulting in a thicker dielectric layer above the area of the substrate.

8. The method of claim 7 , further comprising:
forming at least one first type of semiconductor device over the substrate; and
forming at least one second type of semiconductor device over the remaining blanket layer of semiconductor material.

9. The method of claim 8 , wherein the at least one second type of semiconductor device comprises at least one laterally diffused metal oxide semiconductor (LDMOS) detector.

10. The method of claim 8 , wherein the at least one second type of semiconductor device comprises at least one transistor, the at least one transistor comprising work-function material in a gate structure.

11. The method of claim 7 , further comprising forming a protective layer over the layer of dielectric material prior to removing the at least one portion.

12. The method of claim 7 , further comprising:
forming a second blanket dielectric layer over the structure after the removing; and
forming a layer of dielectric material over the second blanket dielectric layer above the area of the substrate.

13. The method of claim 7 , further comprising, after removing the common portion and before forming the layer of dielectric material, forming a layer of semiconductor material on the area of the substrate such that a top surface of the structure is planar, and wherein forming the layer of dielectric material comprises forming the layer of dielectric material on the layer of semiconductor material.

14. The method of claim 13 , wherein forming the layer of semiconductor material comprises forming epitaxial semiconductor material.

15. The method of claim 13 , further comprising forming a protective layer over the layer of dielectric material prior to removing the at least one portion.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Liu Bingwu

Classifications

• H01L21/84

  Electricity · mapped topic

• H01L21/8234

  Electricity · mapped topic

• H01L27/1207 Primary

  Electricity · mapped topic

• H10D86/01

  Manufacture or treatment · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title