Enhanced discrete-time feedforward equalizer

Patent metadata

Field	Value
Publication number	US-11539555-B2
Application number	US-202017095869-A
Country	US
Kind code	B2
Filing date	Nov 12, 2020
Priority date	Jun 29, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

First claim

What is claimed is:

1. A feedforward equalizer (FFE), comprising:
a set of N FFE taps coupled together in parallel, wherein each FFE tap of the N FFE taps comprises:
a unique sample-and-hold (S/H) circuit configured to generate a unique time-delayed signal; and
a unique transconductance stage configured to generate a unique transconductance output based on the unique time-delayed signal;

a filter coupled between the (N−1)th FFE tap and the Nth FFE tap; and
a summer coupled to an output of the set of N FFE taps.

2. The FFE of claim 1 , wherein the filter comprises a first order high pass filter such that coefficients greater than N have an opposite polarity to an Nth coefficient.

3. The FFE of claim 1 , wherein the filter comprises a first order low pass filter such that coefficients greater than N have a same polarity as an Nth coefficient.

4. The FFE of claim 1 , wherein a particular S/H circuit in a particular FFE tap comprises a first track-and-hold (T/H) circuit and a second T/H circuit.

5. The FFE of claim 4 , wherein at least one of the first and second T/H circuits in the particular S/H circuit comprises:
a preamplifier; and
a switched emitter follower.

6. The FFE of claim 5 , wherein the preamplifier comprises a degeneration capacitor, wherein a capacitance of the degeneration capacitor is chosen to extend a bandwidth of the preamplifier.

7. The FFE of claim 5 , wherein the at least one of the first and second T/H circuits further comprises a feedforward capacitor coupled between the preamplifier and the switched emitter follower, wherein a capacitance of the feedforward capacitor is chosen to reduce hold mode feedthrough.

8. The FFE of claim 5 , wherein the particular FFE tap is the Nth FFE tap, wherein the particular S/H circuit is the Nth S/H circuit, wherein the at least one of the first and second T/H circuits is the first T/H circuit, wherein the preamplifier further comprises the filter coupled between the (N−1)th FFE tap and the Nth FFE tap.

9. The FFE of claim 8 , wherein the preamplifier comprises a filtering capacitor.

10. An apparatus, comprising:
a set of N sample-and-hold (S/H) circuits coupled together in series;
a filter coupled between the (N−1)th S/H circuit and the Nth S/H circuit;
a set of N transconductance stages, wherein each transconductance stage is coupled to an output of a unique S/H circuit in the N S/H circuits; and
a summer coupled to outputs of the N transconductance stages.

11. The apparatus of claim 10 , wherein the filter comprises a first order high pass filter such that coefficients greater than N have an opposite polarity to an Nth coefficient.

12. The apparatus of claim 10 , wherein the filter comprises a first order low pass filter such that coefficients greater than N have a same polarity as an Nth coefficient.

13. The apparatus of claim 10 , wherein a S/H circuit in the set of N S/H circuits comprises a track-and-hold (T/H) circuit.

14. The apparatus of claim 10 , wherein the T/H circuit comprises:
a preamplifier coupled to an input of the T/H circuit; and
a switched emitter follower coupled to an output of the preamplifier and to an output of the T/H circuit.

15. The apparatus of claim 14 , wherein the preamplifier comprises a degeneration capacitor, and wherein the T/H circuit further comprises a feedforward capacitor coupled between the preamplifier and the switched emitter follower.

16. The apparatus of claim 14 , wherein the S/H circuit is the Nth S/H circuit, wherein the preamplifier further comprises the filter.

17. A feedforward equalizer (FFE), comprising:
a first sample and hold (S/H) circuit configured to receive an input signal and a clock signal and to output a first retimed signal;
a first amplifier configured to receive the first retimed signal and to output a first weighted signal;
a second S/H circuit configured to receive the first retimed signal and the clock signal and to output a second retimed signal;
a second amplifier configured to receive the second retimed signal and to output a second weighted signal;
a filter configured to receive the second retimed signal and to output a filtered signal;
a third S/H circuit configured to receive the filtered signal and the clock signal and to output a third retimed signal;
a third amplifier configured to receive the third retimed signal and to output a third weighted signal; and
a summer configured to combine the first, second, and third weighted signals.

18. The FFE of claim 17 , wherein the filter comprises a first order high pass filter such that an equalization of the FFE is greater than three taps, wherein higher order coefficients beyond a third coefficient have an opposite polarity to the third coefficient.

19. The FFE of claim 17 , wherein the filter comprises a first order low pass filter such that an equalization of the FFE is greater than three taps, wherein higher order coefficients beyond a third coefficient have a same polarity as the third coefficient.

20. The FFE of claim 17 , wherein the third S/H circuit comprises a master track-and-hold (T/H) circuit and a slave T/H circuit.

21. The FFE of claim 20 , wherein the master T/H circuit comprises:
a preamplifier, wherein the preamplifier comprises the filter; and
a switched emitter follower.

22. The FFE of claim 21 , wherein the preamplifier further comprises a degeneration capacitor, wherein the master T/H circuit further comprises a feedforward capacitor coupled between the preamplifier and the switched emitter follower.

Assignees

• Texas Instruments Inc

Inventors

• Manian Abishek
• Vijayan Ashwin Kottilvalappil
• Rane Amit
• Roshan Zamir Ashkan

Classifications

• G05F1/561

  Voltage to current converters (amplifiers H03F) · CPC title

• H04L25/03261 Primary

  with impulse-response shortening filters · CPC title

• H03F2203/45488

  the CSC being a pi circuit and a capacitor being used at the place of the resistor · CPC title

• H03F3/183

  with semiconductor devices only · CPC title

• H03H15/02

  using analogue shift registers · CPC title