Track-and-hold charge pump and PLL

Patent metadata

Field	Value
Publication number	US-10523218-B2
Application number	US-201715490096-A
Country	US
Kind code	B2
Filing date	Apr 18, 2017
Priority date	Apr 18, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Track-and-hold charge pumps and PLL are provided. A track-and-hold charge pump includes a track-and-hold circuit, a transconductance amplifier, a pulse width modulator (PWM), and a pumping switch coupled to the transconductance amplifier. The track-and-hold circuit samples an input signal according to a reference clock. The transconductance amplifier converts the sampled input signal into a current. The PWM provides a PWM signal according to the reference clock. The pumping switch is controlled by the PWM signal, to provide an output current according to the current.

First claim

What is claimed is:

1. A phase-locked loop (PLL), comprising:
a voltage-controlled oscillator (VCO) configured to provide an output clock according to a control voltage;
a low pass filter (LPF) configured to filter a pumping signal corresponding to a pumping current to provide the control voltage;
a frequency divider configured to divide the output clock to provide a feedback signal; and
a track-and-hold charge pump coupled to the LPF configured to provide the pumping current according to a reference clock and the feedback signal;
wherein the track-and-hold charge pump comprises:
a pumping switch coupled to the LPF; and
a pulse width modulator (PWM) configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

2. The PLL as claimed in claim 1 , wherein a bandwidth of the PLL is changed when a pulse width of the PWM signal, a transconductance of a transconductance amplifier, or a slew rate of the feedback signal is changed.

3. The PLL as claimed in claim 1 , wherein the track-and-hold charge pump further comprises:
a track-and-hold circuit coupled to the frequency divider configured to sample the feedback signal according to the reference clock; and
a transconductance amplifier (OTA) configured to convert the sampled feedback signal into a current,
wherein the pumping switch is coupled between the transconductance amplifier and the LPF, and the pumping switch is controlled by the PWM signal to provide the pumping current according to the current.

4. The PLL as claimed in claim 1 , further comprising:
a converter coupled to the LPF configured to convert the pumping signal into a logic signal; and
a bandwidth tracking circuit configured to provide a control signal to control the pumping signal of the PLL according to the logic signal,
wherein the logic signal indicates whether the pumping switch is turned on by the PWM signal.

5. The PLL as claimed in claim 4 , wherein the converter comprises:
a string of self-biased inverters;
a capacitive element coupled between the LPF and an input self-biased inverter of the string of self-biased inverters; and
a string of inverters coupled between the string of self-biased inverters and the bandwidth tracking circuit.

6. The PLL as claimed in claim 5 , wherein the string of self-biased inverters amplifies an alternating current (AC) component of the pumping signal to obtain an amplified signal, and the string of inverters converts the amplified signal into the logic signal.

7. The PLL as claimed in claim 4 , wherein the bandwidth tracking circuit comprises:
a plurality of flip-flops coupled in series, wherein the logic signal is input to a first flip-flop of the flip-flops;
a plurality of first multipliers corresponding to the flip-flops, wherein each first multiplier multiplies the logic signal by an output of the corresponding flip-flop to provide a first value;
an adder configured to sum the first values to obtain a second value;
an integrator configured to integrate the second value; and
a second multiplier configured to multiply the integrated second value by a weight value to provide the control signal, so as to change a pulse width of the PWM signal, a transconductance of the transconductance amplifier, or a slew rate of the feedback signal.

8. A phase-locked loop (PLL), comprising:
a voltage-controlled oscillator (VCO) configured to provide an output clock according to a control voltage;
a low pass filter (LPF) configured to filter a pumping signal corresponding to a pumping current to provide the control voltage;
a frequency divider configured to divide the output clock to provide a feedback signal;
a track-and-hold charge pump coupled to the LPF configured to provide the pumping current via a pumping switch according to a reference signal and the feedback signal; and
a bandwidth calibration circuit coupled to the LPF configured to provide a control signal to the track-and-hold charge pump, so as to adjust the pumping current.

9. The PLL as claimed in claim 8 , wherein the bandwidth calibration circuit comprises:
a converter coupled to the LPF configured to convert the pumping signal into a logic signal; and
a bandwidth tracking circuit configured to provide the control signal to control the pumping signal according to the logic signal,
wherein the logic signal indicates whether the pumping switch is turned on.

10. The PLL as claimed in claim 9 , wherein the converter comprises:
a string of self-biased inverters;
a capacitive element coupled between the LPF and an input self-biased inverter of the string of self-biased inverters; and
a string of inverters coupled between the string of self-biased inverters and the bandwidth tracking circuit.

11. The PLL as claimed in claim 10 , wherein the string of self-biased inverters amplifies an alternating current (AC) component of the pumping signal to obtain an amplified signal, and the string of inverters converts the amplified signal into the logic signal.

12. The PLL as claimed in claim 9 , wherein the bandwidth tracking circuit comprises:
a plurality of flip-flops coupled in series, wherein the logic signal is input to a first flip-flop of the flip-flops;
a plurality of first multipliers corresponding to the flip-flops, wherein each first multiplier multiplies the logic signal by an output of the corresponding flip-flop to provide a first value;
an adder configured to sum the first values to obtain a second value;
an integrator configured to integrate the second value; and
a second multiplier configured to multiply the integrated second value by a weight value to provide the control signal.

13. The PLL as claimed in claim 8 , wherein the track-and-hold charge pump comprises:
a track-and-hold circuit coupled to the frequency divider configured to sample the feedback signal according to the reference signal;
a transconductance amplifier (OTA) configured to convert the sampled feedback signal into a current; and
a pulse width modulator (PWM) configured to provide a PWM signal to control the pumping switch according to the reference signal, so as to provide the pumping signal according to the current,
wherein the pumping switch is coupled between the transconductance amplifier and LPF.

14. The PLL as claimed in claim 13 , wherein the PWM modifies a pulse width of the PWM signal according to the control signal, and magnitude of the pumping signal is changed when a pulse width of the PWM signal is changed by the control signal.

15. The PLL as claimed in claim 13 , wherein the transconductance amplifier converts the sampled input signal into the current according to a transconductance, and magnitude of the pumping signal is changed when the transconductance is changed by the control signal.

16. The PLL as claimed in claim 13 , wherein the track-and-hold charge pump further comprises:
a buffer coupled to the track-and-hold circuit configured to provide the input signal with a slew rate to the track-and-hold circuit,
wherein magnitude of the pumping signal is changed when the slew rate is changed by the control signal.

17. A phase-locked loop (PLL), comprising:
a voltage-controlled oscillator (VCO) configured to provide an output clock according to a control voltage;
a low pass filter (LPF) configured to filter a pumping signal corresponding to a pumping current to provide the control voltage;
a frequency divider configured to divide the output clock to provide a first feedback signal and a second feedback signal; an

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuan Ting-Kuei
• Hsieh Cheng-Hsiang
• Ko Chen-Ting
• Sheen Ruey-Bin
• Chang Chih-Hsien

Classifications

• H03L7/097

  using a comparator for comparing the voltages obtained from two frequency to voltage converters · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title