Retimer data communication modules

Patent metadata

Field	Value
Publication number	US-10659337-B2
Application number	US-201816115291-A
Country	US
Kind code	B2
Filing date	Aug 28, 2018
Priority date	Aug 28, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.

First claim

What is claimed is:

1. A data communication device comprising:
a host receive section for receiving incoming host data from a host device, the host receive section including a plurality of host receive lanes, the plurality of host receive lanes including a first host receive lane, the first receive lane including a first analog interface and a first pattern checker module;
a host transmit section for transmitting outgoing host data to the host device, the host transmit section including a plurality of host transmit lanes and a host cross point section, the plurality of host transmit lanes including a first host transmit lane, the first host transmit lane including a first buffer and a first pattern generator;
a link monitor section coupled to the host receive section and the host transmit section;
a line receive section for receiving incoming line data from a line device, the line receive section including a plurality of line receive lanes, the plurality of line receive lanes including a first line receive lane, the first line receive lane including a first sequence checker and a first soft FEC decoder;
a line transmit section for transmitting outing line data to the line device, the line transmit section including a plurality of line transmit lanes and a line cross point section, the plurality of line transmit lanes including a first line transmit lane, the first line transmit lane including a first soft FEC encoder; and
a management interface module coupled to the link monitor section;
wherein:
the incoming host data are transmitted to the line device via the host receive section and line transmit section in an egress operation;
the incoming line data are transmitted the host device via the line receive section and the host transmit section in an ingress operation.

2. The device of claim 1 wherein the incoming host data are transmitted back to the host device via the host receive section and host transmit section in host loopback operation.

3. The device of claim 2 wherein the incoming host data pass through the host cross point section.

4. The device of claim 1 wherein the line host data are transmitted back to the line device via the line receive section and line transmit section in line loopback operation.

5. The device of claim 1 wherein the management interface module comprises a management data input/out module.

6. The device of claim 5 wherein the management interface module comprises a microprocessor unit.

7. The device of claim 1 wherein the incoming data pass through the link monitor section during the egress operation.

8. The device of claim 1 wherein the first line receive lane further comprises a digital signal processor.

9. The device of claim 8 wherein the digital signal process is configured to process eye histograms.

10. The device of claim 1 wherein the first sequence checker is configured to perform PRBS check.

11. The device of claim 1 wherein the first line transmit lane further comprises a error injection block.

12. The device of claim 1 wherein the first line transmit lane further comprises a error injection block.

13. A data communication device comprising:
a host receive section for receiving incoming host data from a host device, the host receive section including a plurality of host receive lanes;
a host transmit section for transmitting outgoing host data to the host device, the host transmit section including a plurality of host transmit lanes and a host cross point section;
a line receive section for receiving incoming line data from a line device, the line receive section including a plurality of line receive lanes;
a line transmit section for transmitting outing line data to the line device, the line transmit section including a plurality of line transmit lanes and a line cross point section;
a link monitor section coupled to the host receive section and the line transmit section, the link monitor section being configured to detector errors from the incoming host data and the incoming line data; and
a management interface module coupled to the link monitor section;
wherein:
the incoming host data are transmitted to the line device via the host receive section and line transmit section in an egress operation;
the incoming line data are transmitted the host device via the line receive section and the host transmit section in an ingress operation.

14. The device of claim 13 wherein the link monitor sections analyzes error statistics associated with the incoming host data.

15. The device of claim 13 wherein the line transmit section comprises a test pattern memory block.

16. The device of claim 13 wherein the line transmit section further comprises an analog front end section for transmitting optical signals.

17. The device of claim 13 wherein the host transmit section comprises four slices corresponding to the plurality of host transmit lanes.

18. A data communication device comprising:
a host receive section for receiving incoming host data from a host device, the host receive section including a plurality of host receive lanes, the plurality of host receive lanes including a first host receive lane, the first receive lane including a first analog interface and a first pattern checker module;
a host transmit section for transmitting outgoing host data to the host device, the host transmit section including a plurality of host transmit lanes and a host cross point section, the plurality of host transmit lanes including a first host transmit lane, the first host transmit lane including a first buffer and a first pattern generator;
a link monitor section coupled to the host receive section and the host transmit section;
a line receive section for receiving incoming line data from a line device, the line receive section including a plurality of line receive lanes, the plurality of line receive lanes including a first line receive lane, the first line receive lane including a first sequence checker and a first soft FEC decoder;
a line transmit section for transmitting outing line data to the line device, the line transmit section including a plurality of line transmit lanes and a line cross point section, the plurality of line transmit lanes including a first line transmit lane, the first line transmit lane including a first soft FEC encoder; and
a management interface module coupled to the link monitor section, the management interface module comprising an MDIO block and an MCU block.

19. The device of claim 18 further comprising a storage unit coupled to the management interface, the storage unit comprising instruction for initiating the host receive section.

20. The device of claim 18 wherein the storage unit further comprises instruction for DSP sequencing codes.

Assignees

• Inphi Corp

Inventors

• Riani Jamal
• Farhoodfar Arash
• Bhoja Sudeep
• Setya Tarun

Classifications

• H04L43/50

  Testing arrangements · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title

• H04L43/12 Primary

  Network monitoring probes · CPC title

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H04L43/0823

  Errors, e.g. transmission errors · CPC title