Redriver link testing

Patent metadata

Field	Value
Publication number	US-9692589-B2
Application number	US-201514866925-A
Country	US
Kind code	B2
Filing date	Sep 26, 2015
Priority date	Jul 17, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.

First claim

What is claimed is:

1. An apparatus comprising:
a redriver comprising:
a receiver to receive a signal from a first device, the signal comprising a portion of a defined binary sequence;
a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence;
the LFSR to generate an expected version of the binary sequence from the seed; and
pattern checking logic, implemented at least in part in hardware, to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.

2. The apparatus of claim 1 , wherein the LFSR comprises a Fibonacci LFSR.

3. The apparatus of claim 1 , wherein the signal comprises a link testing signal.

4. The apparatus of claim 3 , wherein the link testing signal comprises a pseudo random binary sequence (PRBS).

5. The apparatus of claim 3 , wherein the link testing signal is used in a loopback session.

6. The apparatus of claim 1 , wherein the redriver further comprises clock and data recovery (CDR) circuitry to recover a clock signal from the signal.

7. The apparatus of claim 1 , wherein the redriver is further to redrive the received signal using redriver circuitry.

8. The apparatus of claim 7 , wherein the redriver circuitry comprises:
receiver pins to receive the signal from the first device;
an amplifier to amplify the signal; and
transmitter pins to transmit the amplified signal to a second device, wherein at least a portion of the signal comprises a loopback test signal.

9. The apparatus of claim 1 , wherein the pattern checking logic is to generate error data in response to detecting that the sequence in subsequent signals does not match the expected version of the binary sequence.

10. The apparatus of claim 9 , wherein the error data is made available to management software through a status register of the redriver.

11. The apparatus of claim 9 , wherein the error data is made available to management software through sideband pins of the redriver.

12. A system comprising:
a first device;
a second device; and
a first redriver, wherein the first device is connected to the second device by a link comprising the first redriver, the first redriver redrives a signal sent from the first device to the second device, and the first redriver comprises:
a first receiver to receive a signal from the first device, the signal comprising a portion of a defined binary sequence;
a first drift buffer to retime the binary sequence and provide a seed to a first linear feedback shift register from the binary sequence;
the first linear feedback shift register (LFSR) to generate an expected version of the binary sequence from the seed;
first pattern checking logic, implemented at least in part in hardware, to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the first linear feedback shift register; and
a transmitter to send the signals received from the first device to a second device.

13. The system of claim 12 , further comprising a second redriver comprising:
a second receiver to receive the signal from the second device, the signal comprising the portion of a defined binary sequence;
a second drift buffer to retime the binary sequence and provide a seed for generation of a copy of the binary sequence;
a second linear feedback shift register to generate an expected version of the binary sequence from the seed;
second pattern checking logic, implemented at least in part in hardware, to compare a sequence in subsequent signals received from the second device with the expected version of the binary sequence generated by the second linear feedback shift register; and
a transmitter to send the signals received from the second device to the first device.

14. The system of claim 12 , wherein the first device comprises the second pattern checking logic, implemented at least in part in said hardware, to check received sequences with the expected binary sequence.

15. The system of claim 14 , wherein the second device comprises third pattern checking logic, implemented at least in part in hardware, to check received sequences with the expected binary sequence.

16. The system of claim 15 , further comprising system management software to assess results generated by the pattern checking logic of any one of the first device, second device, and first redriver.

17. The system of claim 12 , wherein the LFSR comprises a Fibonacci LFSRs.

18. The system of claim 12 , wherein the defined binary sequence comprises a pseudo random binary sequence (PRBS) for a loopback test.

Assignees

• Intel Corp

Inventors

• Iyer Venkatraman
• Spagna Fulvio
• Das Sharma Debendra

Classifications

• H04L1/241 Primary

  using pseudo-errors · CPC title

• H04L25/20 Primary

  Repeater circuits; Relay circuits · CPC title

• H04L7/027 Primary

  extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit · CPC title

• H04L1/243

  at the transmitter, using a loop-back · CPC title