Majority logic gate with input paraelectric capacitors

Patent metadata

Field	Value
Publication number	US-11539368-B1
Application number	US-202117317482-A
Country	US
Kind code	B1
Filing date	May 11, 2021
Priority date	Dec 27, 2019
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

First claim

We claim:

1. An apparatus comprising:
a node;
a first capacitor having a first terminal to receive a first input, and a second terminal coupled to the node;
a second capacitor having a first terminal to receive a second input, and a second terminal coupled to the node;
a third capacitor having a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first capacitor, the second capacitor and the third capacitor comprise a ferroelectric material which is doped; and
a logic having an input and an output, wherein the input of the logic is coupled to the node, wherein the input of the logic has capacitance, and wherein the ferroelectric material is doped with an f-orbital material.

2. The apparatus of claim 1 comprising a fourth capacitor which includes a first terminal coupled to the node and a second terminal coupled to the input of the logic.

3. The apparatus of claim 2 , wherein the fourth capacitor comprises non-linear polar material.

4. The apparatus of claim 1 comprising:
a first transistor coupled to the node and ground, wherein the first transistor is controllable by a first control; and
a second transistor coupled to the input of the logic and the ground, wherein the second transistor is controllable by a second control.

5. The apparatus of claim 1 , comprising:
a first driver to generate the first input;
a second driver to generate the second input; and
a third driver to generate the third input.

6. The apparatus of claim 3 , wherein the non-linear polar material includes one of: a ferroelectric material, a para electric material or a non-linear dielectric.

7. The apparatus of claim 6 , wherein the ferroelectric material includes one of:
Bismuth ferrite (BFO) with a doping material wherein the doping material is one of Lanthanum, or elements from lanthanide series of periodic table;
Lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La or Nb;
a relaxor ferroelectric which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST);
a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;
a hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3;
hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element including one or more of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;
Hafnium oxides of a form, Hf1−x Ex Oy where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
Al(1−x)Sc(x)N, Ga(1−x)Sc(x)N, Al(1−x)Y(x)N or Al(1−x−y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, and wherein ‘x’ is a fraction;
Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.

8. The apparatus of claim 3 , wherein the fourth capacitor comprising non-linear polar material is positioned in a backend of a die, and wherein the logic is positioned in a frontend of the die.

9. The apparatus of claim 1 , wherein the ferroelectric material, which is doped, is a room temperature paraelectric material.

10. The apparatus of claim 9 , wherein the room temperature paraelectric material includes one of: SrTiO 3 , Ba x Sr y TiO 3 , HfZrO 2 , HfSiO, La substituted PbTiO3, or PMN-PT based relaxor ferroelectric.

11. An apparatus comprising:
a node;
a first capacitor having a first terminal to receive a first input, and a second terminal coupled to the node;
a second capacitor having a first terminal to receive a second input, and a second terminal coupled to the node;
a third capacitor having a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first capacitor, the second capacitor and the third capacitor comprise a room temperature paraelectric material; and
a logic having an input and an output, wherein the input of the logic is coupled to the node, and wherein the input of the logic has capacitance.

12. The apparatus of claim 11 , wherein the room temperature paraelectric material includes one of: SrTiO 3 , Ba x Sr y TiO 3 , HfZrO 2 , HfSiO, La substituted PbTiO3, or PMN-PT based relaxor ferroelectric.

13. The apparatus of claim 11 comprising:
a first transistor coupled to the node and ground, wherein the first transistor is controllable by a first control; and
a second transistor coupled to the input of the logic and the ground, wherein the second transistor is controllable by a second control.

14. The apparatus of claim 11 comprising a fourth capacitor which includes a first terminal coupled to the node and a second terminal coupled to the input of the logic.

15. The apparatus of claim 14 , wherein the fourth capacitor comprises non-linear polar material.

16. A system comprising:
a memory;
a processor circuitry to execute one or more instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes:
a node;
a first capacitor having a first terminal to receive a first input, and a second terminal coupled to the node;
a second capacitor having a first terminal to receive a second input, and a second terminal coupled to the node;
a third capacitor having a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first capacitor, the second capacitor and the third capacitor comprise a non-linear material; and
a logic having an input and an output, wherein the input of the logic is coupled to the node, wherein the input of the logic has capacitance, and wherein the processor circuitry comprising:
a first transistor coupled to the node and ground, wherein the first transistor is controllable by a first control; and
a second transistor coupled to the input of the logic and the ground, wherein the second transistor is controllable by a second control.

17. The system of claim 16 , wherein the non-linear material is a room temperature paraelectric material including one of: SrTiO 3 , Ba x Sr y TiO 3 , HfZrO 2 , HfSiO, La substituted PbTiO3, or PMN-PT based relaxor ferroelectric.

18. The system of claim 16 comprising a fourth capacitor which includes a first terminal coupled to the node and a second terminal coupled to the input of the logic.

Assignees

• Kepler Computing Inc

Inventors

• Manipatruni Sasikanth
• Rios Rafael
• Odinaka Ikenna
• Menezes Robert
• Dokania Rajeev Kumar
• Ramesh Ramamoorthy
• Mathuriya Amrita

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/23 Primary

  Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs · CPC title

• H03K19/16

  using saturable magnetic devices · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H03K19/003

  Modifications for increasing the reliability {for protection} · CPC title