Non-volatile memory device which utilizes a pulse applied to a bit line and/or a common source line between read operations to reduce noise

Patent metadata

Field	Value
Publication number	US-11538533-B2
Application number	US-202117233858-A
Country	US
Kind code	B2
Filing date	Apr 19, 2021
Priority date	Sep 7, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line;
a common source line driver configured to supply a common source line voltage to the common source line;
a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines;
a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and
a channel initialization circuit,
wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and
the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines,
wherein the initialization pulse is applied at a time point when a first application of the read voltage ends and application of the initialization pulse ends at a time point when a second application of the read voltage starts.

2. The non-volatile memory device of claim 1 , wherein the channel initialization circuit includes a detector configured to detect noise in the plurality of word lines before the read voltage is applied, and a pulse generator configured to set the common source line voltage and the bit line voltage to the initialization pulse.

3. The non-volatile memory device of claim 2 , wherein the detector sends an initialization pulse generation signal to the pulse generator when the noise is detected.

4. The non-volatile memory device of claim 3 , wherein the pulse generator receives the initialization pulse generation signal, and sets the common source line voltage and the bit line voltage to the initialization pulse.

5. The non-volatile memory device of claim 1 , wherein the channel initialization circuit is disposed inside or outside the control logic circuit.

6. The non-volatile memory device of claim 1 , wherein the channel initialization circuit applies the initialization pulse to the common source line and the at least one bit line during a section between the plurality of read sections, and increases a potential of a channel connected between the common source line and the at least one bit line to an initialization voltage.

7. The non-volatile memory device of claim 6 , wherein the initialization voltage is 0 V.

8. A non-volatile memory device, comprising:
a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line;
a control logic circuit configured to adjust a voltage applied to the plurality of word lines; and
a channel initialization circuit configured to adjust a voltage applied to the plurality of bit lines and the common source line,
wherein the control logic circuit applies a pre-charge voltage to the word lines, on which a read operation is executed, among the plurality of word lines from a first time to a second time, applies a read voltage to the word lines on which the read operation is executed from the second time to a third time, applies the read voltage to the word lines, on which no read operation is executed, among the plurality of word lines from the first time to the third time, and executes a recovery operation on the plurality of word lines from the third time to a fourth time, and
the channel initialization circuit applies an initialization pulse to at least one of the plurality of bit lines and the common source line during at least a period of time between the third time and the fourth time.

9. The non-volatile memory device of claim 8 , wherein the initialization pulse applied at the third time.

10. The non-volatile memory device of claim 8 , wherein application the initialization pulse ends at the fourth time.

11. The non-volatile memory device of claim 8 , wherein the channel initialization circuit includes a detector configured to detect noise occurring in the plurality of word lines before the first time, and a pulse generator configured to set the common source line voltage and the bit line voltage to the initialization pulse.

12. The non-volatile memory device of claim 11 , wherein the detector sends an initialization pulse generation signal to the pulse generator when the noise is detected.

13. The non-volatile memory device of claim 12 , wherein the pulse generator receives the initialization pulse generation signal, and sets the common source line voltage and the bit line voltage to the initialization pulse.

14. The non-volatile memory device of claim 8 , wherein the channel initialization circuit is disposed inside or outside the control logic circuit.

15. The non-volatile memory device of claim 8 , wherein the channel initialization circuit increases a potential of a channel connected between the con non source line and the at least one bit line to an initialization voltage.

16. The non-volatile memory device of claim 15 , wherein the initialization voltage is 0 V.

17. A non-volatile memory device, comprising:
a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of string selection lines, a plurality of ground selection lines, a plurality of bit lines and a common source line;
a row decoder connected to the plurality of word lines, the plurality of string selection lines and the plurality of ground selection lines;
a common source line driver connected to the common source line;
a voltage generator configured to apply a word line voltage to the row decoder;
a page buffer unit connected to the plurality of hit lines; and
a control logic circuit configured to transfer a voltage control signal for adjusting the word line voltage to the voltage generator, transfer a row address signal including word line information, which identifies the word line to which the word line voltage is applied, to the row decoder, transfer a common source line voltage control signal, which is used to control a common source line voltage applied to the common source line, to the common source line driver, transfer a read voltage to be applied to at least two of the plurality of word lines, and transfer a column address signal including bit line information, which identifies the bit line to which a bit line voltage is to be applied, to the page buffer unit,
wherein the control logic circuit includes a channel initialization circuit,
the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and
the channel initialization circuit applies the initialization pulse between a plurality of read sections at which the read voltage is applied to the at least two word lines,
wherein the initialization pulse is applied at a time point when application of the read voltage ends.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Gu Yeon
• Kang Jin-Kyu
• Lee Rae Young
• Park Se Jun
• Lee Jae Duk

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title