Nonvolatile memory device and programming method thereof including common source line feedback during program and verification operation

Patent metadata

Field	Value
Publication number	US-9401210-B2
Application number	US-201514607857-A
Country	US
Kind code	B2
Filing date	Jan 28, 2015
Priority date	May 13, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a CSL driver, and control logic. The memory cell array includes a plurality of memory blocks each having a plurality of strings that are formed in a direction perpendicular to a substrate and are connected between bit lines and a common source line. The CSL driver sets up the common source line with a predetermined voltage and supplies or drains charge to or from the common source line using a voltage level of the common source line as a feedback signal.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory blocks each having a plurality of strings formed in a direction perpendicular to a substrate and connected between bit lines and a common source line;
an address decoder adapted to select one of the plurality of memory blocks based upon an address;
an input/output circuit adapted to store data to be programmed at memory cells connected to a selected one of word lines of a selected memory block, of the plurality of memory blocks, for a program operation and store data read from the memory cells connected to the selected word line for a verification operation;
a common source line driver adapted to set the common source line with a preset voltage, and, selectively drain charge from and supply charge to the common source line using a voltage level of the common source line as a feedback signal; and
control logic adapted to control the address decoder, the input/output circuit, and the common source line driver for the program operation and the verification operation;
wherein the common source line driver stepwise decreases a voltage level of the common source line during a common source line recovery period.

2. The nonvolatile memory device of claim 1 , wherein the common source line driver selectively supplies charge to and drains charge from the common source line as a difference between the preset voltage and the voltage level of the common source line.

3. The nonvolatile memory device of claim 1 , wherein the common source line driver comprises:
a differential amplifier adapted to amplify a reference voltage to adjust the voltage level of the common source line; and
a common source line level control unit including a pull-up unit adapted to supply charge to the common source line and a pull-down unit adapted to drain charge from the common source line.

4. The nonvolatile memory device of claim 1 , wherein an output terminal of the differential amplifier is electrically coupled to the common source line.

5. The nonvolatile memory device of claim 1 , wherein the pull-up unit comprises a first enable transistor and a first control transistor connected in series between a second voltage node, supplied with a second voltage, and the common source line; and wherein the pull-down unit comprises a second enable transistor and a second control transistor connected in series between the common source line and a ground.

6. The nonvolatile memory device of claim 5 , wherein the common source line driver further comprises:
an amplification circuit electrically coupled between the differential amplifier and the common source line level control unit and adapted to control operations of the pull-up and pull-down units.

7. The nonvolatile memory device of claim 5 , wherein the amplification circuit is adapted to turn off at least one of the pull-up unit and the pull-down unit.

8. The nonvolatile memory device of claim 6 , wherein the amplification circuit comprises:
a first transistor string having first to fourth transistors connected in series between a first voltage node, supplied with a first voltage, and a ground; and
a second transistor string having fifth to eighth transistors connected in series between the second voltage node and the ground; and
wherein the first and second transistors have a same resistance value, the second and sixth transistors have a same resistance value, the fourth and eighth transistors have a same resistance value, and the third and seventh transistors have different resistance values.

9. The nonvolatile memory device of claim 8 , wherein a gate of the first control transistor is connected to a node between the second and third transistors; and wherein a gate of the second control transistor is connected to a node between the sixth and seventh transistors.

10. The nonvolatile memory device of claim 1 , wherein the common source line driver further comprises:
a ramping code generator adapted to generate a set code for selectively stepwise increasing and decreasing a voltage level of the common source line; and
a first reference voltage generator adapted to output the reference voltage based upon the set code.

11. The nonvolatile memory device of claim 1 , wherein the common source line recovery period is equal to or shorter than about 4 us after a program execution period.

12. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory blocks each having memory cells coupled with bit lines, word lines and a common source line;
an input/output circuit adapted to store data to be programmed at memory cells coupled to a selected one of the word lines of a selected memory block, of the plurality of memory blocks, for a program operation and store data read from the memory cells coupled to the selected word line for a verification operation;
a common source line driver adapted to set the common source line with a preset voltage, and, selectively drain charge from and supply charge to the common source line using a voltage level of the common source line as a feedback signal; and
control logic adapted to control the input/output circuit and the common source line driver for the program operation and the verification operation;
wherein the common source line driver stepwise decreases a voltage level of the common source line during a common source line recovery period.

13. The nonvolatile memory device of claim 12 , wherein the common source line driver selectively supplies charge to and drains charge from the common source line as a difference between the preset voltage and the voltage level of the common source line.

14. The nonvolatile memory device of claim 12 , wherein the common source line driver comprises:
a differential amplifier adapted to amplify a reference voltage to adjust the voltage level of the common source line; and
a common source line level control unit including a pull-up unit adapted to supply charge to the common source line and a pull-down unit adapted to drain charge from the common source line.

15. The nonvolatile memory device of claim 14 , wherein an output terminal of the differential amplifier is electrically coupled to the common source line.

16. The nonvolatile memory device of claim 14 , wherein the pull-up unit comprises a first enable transistor and a first control transistor connected in series between a second voltage node, supplied with a second voltage, and the common source line; and wherein the pull-down unit comprises a second enable transistor and a second control transistor connected in series between the common source line and a ground.

17. A method of programming a nonvolatile memory device which includes a plurality of strings formed between bit lines and a common source line in a direction perpendicular to a substrate, the method comprising:
setting up the common source line with a preset voltage;
selectively supplying charge to and draining charge from the common source line using a voltage level of the common source line as a feedback signal, including
determining whether the voltage level of the common source line varies,
as a consequence of determining that the voltage level of the common source line varies, determining whether the voltage level of the common source line is higher than the preset voltage,
draining charge from the common source line when the voltage level of the common source line is higher than the preset voltage, and
supplying charge to the common source line when the voltage level of the common source line is lower than the

Assignees

• Kwon Tae-Hong
• Kim Doogon
• Samsung Electronics Co Ltd

Inventors

• Kwon Tae-Hong
• Kim Doogon

Classifications

• G11C16/3436

  Arrangements for verifying correct programming or erasure · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title