Multi-dielectric structure in two-layer embedded trace substrate

Patent metadata

Field	Value
Publication number	US-2021287976-A1
Application number	US-202016819732-A
Country	US
Kind code	A1
Filing date	Mar 16, 2020
Priority date	Mar 16, 2020
Publication date	Sep 16, 2021
Grant date	—

Abstract

Certain aspects of the present disclosure generally relate to an embedded trace substrate having at least two different dielectric layers with different dielectric materials and methods for fabricating the same. One example embedded trace substrate generally includes a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; and a second metal layer disposed below the second dielectric layer.

First claim

1 . An embedded trace substrate comprising:
a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material, wherein the first metal layer is at least partially embedded in the first dielectric layer; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; a second metal layer disposed below the second dielectric layer; and at least one via extending between the first and second metal layers of the embedded trace substrate and across the first and second dielectric layers, wherein a combined thickness of the first dielectric layer and the second dielectric layer between the first and second metal layers is no greater than 70 μm and wherein a size of the at least one via is less than or equal to 70 μm.

2 . The embedded trace substrate of claim 1 , wherein the first dielectric layer has a first thickness and wherein the second dielectric layer has a second thickness, the second thickness being greater than the first thickness.

3 . The embedded trace substrate of claim 2 , wherein the first thickness of the first dielectric layer is between 5 μm and 25 μm.

4 . The embedded trace substrate of claim 2 , wherein the second thickness of the second dielectric layer is between 30 μm and 60 μm.

5 . (canceled)

6 . The embedded trace substrate of claim 1 , wherein the combined thickness of the first dielectric layer and the second dielectric layer between the first and second metal layers is no greater than 55 μm.

7 - 8 . (canceled)

9 . The embedded trace substrate of claim 1 , wherein the second dielectric material of the second dielectric layer is a glass-woven material.

10 . The embedded trace substrate of claim 1 , wherein the second dielectric material of the second dielectric layer is a fiberglass material.

11 . (canceled)

12 . The embedded trace substrate of claim 1 , wherein at least one of the first metal layer or the second metal layer comprises a plurality of traces and wherein a line width/space (L/S) ratio supported by the embedded trace substrate, based on a minimum line width of the traces and a minimum space between adjacent traces, is 6 μm/8 μm.

13 . The embedded trace substrate of claim 1 , further comprising:
a first solder resist layer disposed above the first metal layer; and a second solder resist layer disposed below the second metal layer.

14 - 20 . (canceled)

21 . An embedded trace substrate comprising:
a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material, wherein the first dielectric material of the first dielectric layer comprises solder resist and wherein the first metal layer is at least partially embedded in the first dielectric layer; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; a second metal layer disposed below the second dielectric layer; and at least one via extending between the first and second metal layers of the embedded trace substrate and across the first and second dielectric layers, wherein a combined thickness of the first dielectric layer and the second dielectric layer between the first and second metal layers is no greater than 70 μm and wherein a size of the at least one via is less than or equal to 70 μm.

22 . The embedded trace substrate of claim 21 , wherein the first dielectric layer has a first thickness and wherein the second dielectric layer has a second thickness, the second thickness being greater than the first thickness.

23 . The embedded trace substrate of claim 22 , wherein the first thickness of the first dielectric layer is between 5 μm and 25 μm and wherein the second thickness of the second dielectric layer is between 30 μm and 60 μm.

24 - 26 . (canceled)

27 . The embedded trace substrate of claim 21 , wherein the second dielectric material of the second dielectric layer is a glass-woven material.

28 . The embedded trace substrate of claim 21 , wherein the second dielectric material of the second dielectric layer is a fiberglass material.

29 . The embedded trace substrate of claim 22 , wherein the first thickness of the first dielectric layer is between 5 μm and 25 μm.

30 . The embedded trace substrate of claim 22 , wherein the second thickness of the second dielectric layer is between 30 μm and 60 μm.

31 . The embedded trace substrate of claim 21 , wherein at least one of the first metal layer or the second metal layer comprises a plurality of traces, wherein the embedded trace substrate has a line width/space (L/S) ratio of 6 μm/8 μm, and wherein the L/S ratio is based on a minimum line width of the traces and a minimum space between adjacent traces in the plurality of traces.

32 . The embedded trace substrate of claim 2 , wherein the first thickness of the first dielectric layer is between 5 μm and 25 μm and wherein the second thickness of the second dielectric layer is between 30 μm and 60 μm.

33 . The embedded trace substrate of claim 1 , wherein the first dielectric material of the first dielectric layer comprises Ajinomoto build-up film (ABF) or pre-impregnated (prepreg) material.

Assignees

• Qualcomm Inc

Inventors

• Buot Joan Rey Villarba
• Kang Kuiwon
• Park Joonsuk
• Dhandapani Karthikeyan

Classifications

• H10W70/635 Primary

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title