Interconnect structure of semiconductor device

Patent metadata

Field	Value
Publication number	US-11527476-B2
Application number	US-202117143496-A
Country	US
Kind code	B2
Filing date	Jan 7, 2021
Priority date	Sep 11, 2020
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.

First claim

What is claimed is:

1. A method comprising:
depositing a dielectric layer over a conductive feature;
patterning the dielectric layer to form an opening therein, the opening exposing a first portion of the conductive feature;
depositing a first barrier layer on a sidewall of the opening, wherein the first portion of the conductive feature remains exposed at the end of depositing the first barrier layer;
before depositing the first barrier layer, removing a native oxide layer from the first portion of the conductive feature; and
before depositing the first barrier layer, performing a surfactant soaking process on the first portion of the conductive feature, the surfactant soaking process suppressing a deposition rate of a first barrier material of the first barrier layer over the first portion of the conductive feature.

2. The method of claim 1 , further comprising depositing a second barrier layer over the first barrier layer in the opening, the second barrier layer being in physical contact with the first portion of the conductive feature.

3. The method of claim 2 , wherein the second barrier layer is a non-conformal layer.

4. The method of claim 2 , wherein the first barrier layer is separated from the first portion of the conductive feature by the second barrier layer.

5. The method of claim 1 , wherein the surfactant soaking process forms a surfactant layer over the first portion of the conductive feature.

6. The method of claim 5 , wherein the surfactant layer comprises a monolayer of alkene molecules or a monolayer of alkyne molecules.

7. The method of claim 1 , further comprising:
depositing an adhesion layer over the first barrier layer in the opening, the adhesion layer being in physical contact with the first portion of the conductive feature; and
filling the opening with a conductive material.

8. The method of claim 7 , wherein the adhesion layer is in physical contact with the sidewall of the opening.

9. The method of claim 1 , wherein the first barrier layer is in physical contact with the first portion of the conductive feature.

10. A method comprising:
forming a dielectric layer over a first conductive feature;
forming an opening in the dielectric layer, the opening exposing a first portion of the first conductive feature; and
forming a second conductive feature in the opening, wherein forming the second conductive feature comprises:
performing a surface modification process on a top surface of the first portion of the first conductive feature, the surface modification process suppressing a deposition rate of a first barrier material over the top surface of the first portion of the first conductive feature, wherein performing the surface modification process comprises:
performing an oxide reduction process on the top surface of the first portion of the first conductive feature, the oxide reduction process removing a native oxide layer from the first portion of the first conductive feature; and
performing a surfactant soaking process on the top surface of the first portion of the first conductive feature, the surfactant soaking process forming a surfactant layer over the top surface of the first portion of the first conductive feature; and

selectively depositing a first barrier layer comprising the first barrier material on a sidewall of the opening.

11. The method of claim 10 , wherein the surfactant layer comprises alkene molecules or alkyne molecules.

12. The method of claim 10 , wherein performing the oxide reduction process comprises performing a plasma process on the top surface of the first portion of the first conductive feature.

13. The method of claim 10 , further comprising depositing an adhesion layer over the first barrier layer and on a bottom of the opening, the adhesion layer being in physical contact with the top surface of the first portion of the first conductive feature.

14. The method of claim 13 , wherein the adhesion layer is in physical contact with the sidewall of the opening.

15. The method of claim 10 , further comprising depositing a second barrier layer comprising a second barrier material over the first barrier layer and on a bottom of the opening, the second barrier layer being in physical contact with the top surface of the first portion of the first conductive feature.

16. The method of claim 15 , wherein the second barrier layer is in physical contact with the sidewall of the opening.

17. A semiconductor structure comprising:
a first conductive feature, a top surface of the first conductive feature having a first region and a second region different from the first region;
a dielectric layer over the first conductive feature, wherein the dielectric layer covers the first region of the top surface of the first conductive feature, and wherein the dielectric layer does not cover the second region of the top surface of the first conductive feature; and
a second conductive feature within the dielectric layer and in electrical contact with the first conductive feature, the second conductive feature comprising:
a conductive material;
a first barrier layer interposed between a sidewall of the conductive material and a sidewall of the dielectric layer, wherein the first barrier layer does not cover the second region of the top surface of the first conductive feature; and
an adhesion layer interposed between the sidewall of the conductive material and the first barrier layer, wherein the adhesion layer covers the second region of the top surface of the first conductive feature, and wherein the adhesion layer is in physical contact with the sidewall of the dielectric layer.

18. The semiconductor structure of claim 17 , wherein the adhesion layer comprises cobalt, ruthenium, an alloy thereof, a combination thereof, or a multilayer thereof.

19. The semiconductor structure of claim 17 , wherein the first barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or a multilayer thereof.

20. The semiconductor structure of claim 17 , wherein the first conductive feature is a conductive line and the second conductive feature is a conductive via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Yao-Min
• Kuo Chia-Pang
• Huang Chien Chung
• Chang Chih-Yi
• Lee Ya-Lien
• Lin Chun-Chieh
• Su Hung-Wen
• Tsai Ming-Hsing

Classifications

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title