Metal oxide semiconductor field-effect transistor (MOSFET) devices and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-11522064-B2
Application number	US-202117206832-A
Country	US
Kind code	B2
Filing date	Mar 19, 2021
Priority date	Apr 28, 2020
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

Provided are metal oxide field-effect transistor (MOSFET) devices having a metal gate structure, in which a work function of the metal gate structure is uniform along a length direction of a channel, and manufacturing methods thereof. The MOSFET devices include a semiconductor substrate, an active area on the semiconductor substrate and extending in a first direction, and a gate structure on the semiconductor substrate. The gate structure extends across the active area in a second direction that traverses the first direction and comprises a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer, which are sequentially stacked on the active area. A lower surface of the WFC layer may be longer than a first interface between a lower surface of the first metal layer and an upper surface of the high-k layer in the first direction.

First claim

What is claimed is:

1. A metal oxide field-effect transistor (MOSFET) device comprising:
a semiconductor substrate;
an active area on the semiconductor substrate and extending in a first direction; and
a gate structure on the semiconductor substrate, the gate structure extending across the active area in a second direction that traverses the first direction and comprising an interface layer, a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer, which are sequentially stacked on the active area, and each of the high-k layer, the first metal layer, the WFC layer, and the second metal layer comprising a lower surface facing the semiconductor substrate and an upper surface opposite the lower surface,
wherein the lower surface of the WFC layer is longer than a first interface between the lower surface of the first metal layer and the upper surface of the high-k layer in the first direction.

2. The MOSFET device of claim 1 , wherein the WFC layer comprises a WFC material, and a concentration of the WFC material on the first interface is uniform along the first direction.

3. The MOSFET device of claim 1 , wherein each of the high-k layer, the first metal layer, and the WFC layer has a uniform thickness along the first direction,
the high-k layer is shorter than the first metal layer in the first direction, and
lengths of the first metal layer and the WFC layer in the first direction are substantially equal to each other.

4. The MOSFET device of claim 3 , wherein the active area comprises a fin structure protruding from the semiconductor substrate, and the fin structure comprises side surfaces that are spaced apart from each other in the second direction,
the gate structure extends on an upper surface of the fin structure and both the side surfaces of the fin structure, and the gate structure comprises side surfaces that are spaced apart from each other in the first direction,
spacers are respectively on the side surfaces of the gate structure, and
inner side surfaces of the spacers have respective steps adjacent the first interface.

5. The MOSFET device of claim 1 , wherein each of the first metal layer and the second metal layer comprises side surfaces that are spaced apart from each other in the first direction,
the high-k layer comprises a bottom portion extending on the lower surface of the first metal layer and protruding portions extending respectively on the side surfaces of the first metal layer,
the WFC layer comprises a bottom portion extending on the lower surface of the second metal layer and protruding portions extending respectively on the side surfaces of the second metal layer, and
the lower surface of the WFC layer is in contact with the upper surface of the first metal layer and upper surfaces of the protruding portions of the high-k layer.

6. The MOSFET device of claim 5 , wherein the active area comprises a fin structure protruding from the semiconductor substrate, and the fin structure comprises side surfaces that are spaced apart from each other in the second direction,
the gate structure extends on an upper surface of the fin structure and both the side surfaces of the fin structure, and the gate structure comprises side surfaces that are spaced apart from each other in the first direction,
spacers are respectively on the side surfaces of the gate structure, and
side surfaces of the interface layer, the high-k layer, and the WFC layer are coplanar with each other and are in contact with inner side surfaces of the spacers.

7. The MOSFET device of claim 1 , wherein the WFC layer comprises aluminum (Al).

8. The MOSFET device of claim 1 , wherein lengths of the first metal layer and the WFC layer are substantially equal to each other in the first direction, and the lower surface of the WFC layer forms a second interface with the upper surface of the first metal layer, and
the second interface is longer than the first interface in the first direction.

9. The MOSFET device of claim 1 , wherein the gate structure comprises side surfaces that are spaced apart from each other in the first direction, and
the MOSFET device further comprises spacers that are respectively on the side surfaces of the gate structure, inner side surfaces of the spacers each have a step or a planar shape adjacent the first interface.

10. A metal oxide field-effect transistor (MOSFET) device comprising:
a semiconductor substrate;
an active area protruding from the semiconductor substrate and extending in a first direction;
a gate structure on the semiconductor substrate, the gate structure extending in a second direction that traverses the first direction and covering at least a portion of the active area, the gate structure comprising an interface layer, a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer, which are sequentially stacked on the active area, and each of the high-k layer, the first metal layer, the work function control (WFC) layer, and the second metal layer comprising a lower surface facing the semiconductor substrate and an upper surface opposite the lower surface; and
source and drain areas respectively on side surfaces of the gate structure, the side surfaces of the gate structure being spaced apart from each other in the first direction,
wherein the lower surface of the WFC layer is longer than a first interface between the lower surface of the first metal layer and the upper surface of the high-k layer in the first direction.

11. The MOSFET device of claim 10 , wherein each of the high-k layer, the first metal layer, and the WFC layer has a uniform thickness along the first direction,
the high-k layer is shorter than the first metal layer in the first direction,
lengths of the first metal layer and the WFC layer are substantially equal to each other in the first direction, and the lower surface of the WFC layer forms a second interface with the upper surface of the first metal layer, and
the second interface is longer than the first interface in the first direction.

12. The MOSFET device of claim 10 , wherein each of the first metal layer and the second metal layer comprises side surfaces that are spaced apart from each other in the first direction,
the high-k layer has a U-shape and covers the lower surface of the first metal layer and both the side surfaces of the first metal layer,
the WFC layer has a U-shape and covers the lower surface of the second metal layer and both the side surfaces of the second metal layer,
the lower surface of the WFC layer forms a second interface with the upper surface of the first metal layer and uppermost surfaces of the high-k layer, and
the second interface is longer than the first direction in the first direction.

13. The MOSFET device of claim 10 , further comprising spacers that are respectively on the side surfaces of the gate structure,
wherein inner side surfaces of the spacers each have a step or a planar shape adjacent the first interface.

14. The MOSFET device of claim 10 , wherein the WFC layer comprises titanium aluminum carbide (TiAlC), and
each of the first metal layer and the second metal layer comprises titanium nitride (TiN).

15. A metal oxide field-effect transistor (MOSFET) device comprising:
a substrate;
an active area on the substrate;
a gate structure on the active area, the gate structure comprising a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer that are sequentially stacked on the active area, and each of the high-k layer, the first metal layer, the WFC layer, and the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Sangjun
• Kwon Uihui
• Kim Seongnam
• Ahn Hyoshin

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic