Three-dimensional (3D) semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11521981-B2
Application number	US-202017095821-A
Country	US
Kind code	B2
Filing date	Nov 12, 2020
Priority date	May 18, 2020
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device comprising:
a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first row decoder region and the second row decoder region;
a first electrode structure and a second electrode structure on the peripheral circuit structure, wherein the first electrode structure and the second electrode structure are spaced apart in a first direction and each respectively includes stacked electrodes;
a mold structure on the peripheral circuit structure, wherein the mold structure is disposed between the first electrode structure and the second electrode structure and includes stacked sacrificial layers;
vertical channel structures penetrating the first electrode structure and the second electrode structure;
a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure; and
a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern,
wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

2. The 3D semiconductor memory device of claim 1 , further comprising:
a dummy structure penetrating the mold structure,
wherein the dummy structure includes at least one same material as the vertical channel structure.

3. The 3D semiconductor memory device of claim 1 , further comprising:
a dummy contact penetrating the mold structure,
wherein the dummy contact does not extend to the peripheral circuit structure.

4. The 3D semiconductor memory device of claim 1 , further comprising:
a through-contact penetrating the mold structure to extend to the peripheral circuit structure,
wherein the control circuit region includes peripheral transistors and lower interconnection lines on the peripheral transistors, and
the through-contact connects an uppermost one of the lower interconnection lines.

5. The 3D semiconductor memory device of claim 1 , further comprising:
a first lower semiconductor layer between the peripheral circuit structure and the first electrode structure; and
a second lower semiconductor layer between the peripheral circuit structure and the second electrode structure,
wherein the first lower semiconductor layer and the second lower semiconductor layer are spaced apart in the first direction.

6. The 3D semiconductor memory device of claim 5 , further comprising:
a third lower semiconductor layer between the peripheral circuit structure and the mold structure;
a through-contact penetrating the mold structure to connect the third lower semiconductor layer; and
a ground line on the through-contact and electrically connecting the through-contact.

7. The 3D semiconductor memory device of claim 1 , wherein the sacrificial layer of the mold structure physically connects an electrode of the first electrode structure to an electrode of the second electrode structure.

8. The 3D semiconductor memory device of claim 1 , wherein the first row decoder region is adjacent to a side of the first electrode structure, and
the second row decoder region is adjacent to a side of the second electrode structure.

9. The 3D semiconductor memory device of claim 1 , wherein the control circuit region comprises:
a first peripheral transistor provided under the first electrode structure;
a second peripheral transistor provided under the second electrode structure; and
a lower interconnection line crossing under the mold structure,
wherein the first peripheral transistor electrically connects the second peripheral transistor through the lower interconnection line.

10. The 3D semiconductor memory device of claim 1 , wherein a level of a bottom surface of the separation insulating pattern is different from a level of a bottom surface of the separation structure.

11. The 3D semiconductor memory device of claim 1 , wherein each of the vertical channel structures comprises:
a vertical semiconductor pattern; and
a vertical insulating pattern disposed between the vertical semiconductor pattern and the stacked electrodes,
wherein the vertical insulating pattern includes a data storage layer.

12. A three-dimensional (3D) semiconductor memory device comprising:
a substrate;
an electrode structure including electrodes stacked on the substrate;
a mold structure intersecting the electrode structure and extending in a first direction, the mold structure dividing the electrode structure into a first electrode structure and a second electrode structure in a second direction and extending in the first direction;
vertical channel structures penetrating the first electrode structure and the second electrode structure;
a separation insulating pattern provided between the first electrode structure and the mold structure, and penetrating the mold structure; and
a separation structure intersecting the first electrode structure in the second direction and extending to the separation insulating pattern,
wherein the mold structure comprises stacked sacrificial layers respectively disposed at same levels as the stacked electrodes, and
an end of the separation structure is surrounded by the separation insulating pattern when viewed in plan.

13. The 3D semiconductor memory device of claim 12 , further comprising:
a peripheral circuit structure provided under the substrate,
wherein the peripheral circuit structure includes a first row decoder region, a second row decoder region, and a control circuit region between the first row decoder region and the second row decoder region,
wherein the first row decoder region is adjacent to a side of the first electrode structure, and the second row decoder region is adjacent to a side of the second electrode structure.

14. The 3D semiconductor memory device of claim 13 , wherein the control circuit region comprises:
a first peripheral transistor provided under the first electrode structure;
a second peripheral transistor provided under the second electrode structure; and
a lower interconnection line crossing under the mold structure,
wherein the first peripheral transistor is electrically connects the second peripheral transistor through the lower interconnection line.

15. The 3D semiconductor memory device of claim 12 , further comprising:
a dummy structure penetrating the mold structure,
wherein the dummy structure includes at least a same material as the vertical channel structure.

16. The 3D semiconductor memory device of claim 12 , further comprising:
a through-contact penetrating the mold structure; and
a ground line disposed on the through-contact and electrically connecting the through-contact,
wherein the substrate comprises:
a first lower semiconductor layer under the first electrode structure;
a second lower semiconductor layer under the second electrode structure; and
a third lower semiconductor layer under the mold structure,

wherein the through-contact is connected to the third lower semiconductor layer, such that the ground line electrically connects the third lower semiconductor layer.

17. A three-dimensional (3D) semiconductor memory device comprising:
a first substrate;
a peripheral circuit structure on the first substrate, the peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first row decoder region and th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Kwangyoung
• Jo Sangyoun
• Kanamori Kohji
• Han Jeehoon

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• H01L27/11534

  Electricity · mapped topic

• H01L27/11573 Primary

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic