Electronic device including a semiconductor memory unit that includes cell mats of a plurality of planes vertically stacked

Patent metadata

Field	Value
Publication number	US-9377955-B2
Application number	US-201414449062-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Mar 11, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. Each plane includes one or more cell mats. Each cell mat includes lower lines, upper lines crossing the lower lines, and variable resistance elements positioned in intersection regions of the lower lines and the upper lines, respectively. Lower contacts are coupled to the lower lines, respectively, and, in a plan view, overlap with a boundary region between half of the upper lines and the other half number of the upper lines. Upper contacts are coupled to the upper lines, respectively, and overlap with a boundary region between a half number of the lower lines and the other half number of the lower lines. One cell mat of an upper plane is vertically stacked over a lower plane to overlap with two adjacent cell mats of the lower plane.

First claim

What is claimed is:

1. An electronic device comprising a semiconductor memory unit, the semiconductor memory unit comprising:
first to T th planes vertically stacked over a substrate, each of the first to T th planes including one or more cell mats that are horizontally arranged in each plane, T being a natural number greater than or equal to 2,
wherein each of t th cell mats of a t th plane includes t th lower lines extending in a first direction, t th upper lines disposed over the t th lower lines and extending in a second direction crossing the first direction, and t th variable resistance elements disposed between the t th lower lines and the t th upper lines and disposed in intersection regions of the t th lower lines and the t th upper lines, respectively, t being a natural number in a range of 1 to T, and
wherein each of (t+1) th cell mats of a (t+1) th plane overlaps with a first half of one of two t th cell mats that are adjacent to each other in the first direction and overlaps with a second half of the other of the two adjacent t th cell mats, the second half of the other of the two adjacent t th cell mats being adjacent to the first half of one of the two t th cell mats in the first direction, and said each of the (t+1) th cell mats including t th upper lines disposed in the first half of one of the two t th cell mats and the second half of the other of the two adjacent t th cell mats as (t+1) th lower lines, (t+1) th upper lines disposed over the (t+1) th lower lines and extending in the first direction, and (t+1) th variable resistance elements disposed between the t th upper lines and the (t+1) th upper lines and disposed in intersection regions of the t th upper lines and the (t+1) th upper lines;
a t th lower contact coupled to a corresponding one of the t th lower lines and overlapping with a middle portion of the corresponding one of the T th lower lines;
a t th upper contact coupled to a corresponding one of the t th upper lines and overlapping with a middle portion of the corresponding one of the t th upper lines; and
a (t+1) th upper contact coupled to a corresponding one of the (t+1) th upper lines and overlapping with a middle portion of the corresponding one of the (t+1) th upper lines,
wherein a number of the t th variable resistance elements disposed on one side of the t th lower contact is the same as a number of the t th variable resistance elements disposed on the other side of the t th lower contact,
wherein a number of the t th variable resistance elements disposed on one side of the t th upper contact is the same as a number of the t th variable resistance elements disposed on the other side of the t th upper contact,
wherein a number of the (t+1) th variable resistance elements disposed on one side of the t th upper contact is the same as a number of the (t+1) th variable resistance elements disposed on the other side of the t th upper contact, and
wherein a number of the (t+1) th variable resistance elements disposed on one side of the (t+1) th upper contact is the same as a number of the (t+1) th variable resistance elements disposed on the other side of the (t+1) th upper contact.

2. The electronic device according to claim 1 , wherein the (t+1) th upper contact is positioned between the two adjacent t th cell mats.

3. The electronic device according to claim 1 , wherein a combination of the t th lower contact and the t th lower line, a combination of the t th upper contact and the t th upper line, and a combination of the (t+1) th upper contact and the (t+1) th upper line have T-shaped cross-sections, respectively.

4. The electronic device according to claim 1 , wherein each of the t th cell mat and the (t+1) th cell mat is divided into four quadrants in the first and second directions, and
wherein the t th lower contact, the t th upper contact, and the (t+1) th upper contact are positioned at boundaries of the four quadrants.

5. The electronic device according to claim 1 , wherein, among the first to Tth planes, (4n+1) th planes overlap with each other, (4n+2) th planes overlap with each other, (4n+3) th planes overlap with each other, and (4n+4) th planes overlap with each other, in a plan view, n being 0 or a positive integer.

6. The electronic device according to claim 1 , wherein the semiconductor memory unit further comprises:
a selection element interposed between the t th variable resistance element and the t th lower or upper line or between the t th variable resistance element and each of the t th lower and upper lines; and
a selection element interposed between the (t+1) th variable resistance element and the t th or (t+1) th upper line or between the (t+1) th variable resistance element and each of the t th and (t+1) th upper lines.

7. The electronic device according to claim 1 , wherein a (t+2) th cell mat of a (t+2) th plane overlaps with a first quadrant of a first one of four adjacent t th cell mats which are adjacent to each other in the first and second directions, a second quadrant of a second one of the four adjacent t th cell mats, a third quadrant of a third one of the four adjacent t th cell mats, and a fourth quadrant of a fourth one of the four adjacent t th cell mats, the first to fourth quadrants being adjacent to each other in the first and second directions, and
wherein a (t+3) th cell mat of a (t+3) th plane overlaps with a first half of one of two t th cell mats which are adjacent to each other in the second direction and a second half of the other of said two adjacent t th cell mats, the second half being adjacent to the first half in the second direction.

8. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an external device, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory unit is a part of the memory unit in the microprocessor.

9. The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an external device, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory unit is a part of the cache memory unit in the processor.

10. The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured

Assignees

• Sk Hynix Inc

Inventors

• Lee Seung-Hwan
• Lee Hyun-Jeong

Classifications

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L45/08

  Electricity · mapped topic

• H01L45/141

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic