Processor and memory communication in a stacked memory system
US-2024411709-A1 · Dec 12, 2024 · US
US9019739B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9019739-B2 |
| Application number | US-201414152440-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 10, 2014 |
| Priority date | Jan 11, 2013 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.
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What is claimed is: 1. A three-dimensional semiconductor device, comprising: a memory cell array including memory cells that are arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; a string selection li…
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