Wafer alignment markers, systems, and related methods

US11520240B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11520240-B2
Application numberUS-202117314410-A
CountryUS
Kind codeB2
Filing dateMay 7, 2021
Priority dateSep 5, 2018
Publication dateDec 6, 2022
Grant dateDec 6, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

First claim

Opening claim text (preview).

What is claimed is: 1. An alignment system, comprising: a substrate support for supporting a wafer; a sensor movable over the wafer and configured to detect magnetic attributes of alignment markers within the wafer; and a controller operably coupled to the substrate support and sensor, the controller comprising: at least one processor; and at least one non-transitory computer-readable storage medium storing instructions thereon that, when executed by the at least one processor, cause the controller to: receive data related to detected magnetic attributes of the alignment markers from the sensor; and responsive to the received data, determine locations of the alignment markers within the wafer. 2. The alignment system of claim 1 , wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to determine locations of the alignment markers within the wafer relative to an ideal grid. 3. The alignment system of claim 2 , wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to calculate a geometrical transformation model for aligning the wafer relative to the ideal grid. 4. The alignment system of claim 3 , wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to align the wafer using the substrate support based at least partially on the geometrical transformation model. 5. The alignment system of claim 3 , wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to align the wafer using the substrate support responsive to the determined locations of the alignment markers. 6. The alignment system of claim 1 , wherein the sensor is selected from the group consisting of a MFM probe, a SQUID, or VSM. 7. The alignment system of claim 1 , wherein the sensor is selected from the group consisting of a Hall Effect sensor, a GMR sensor, a TMR sensor, an EMR sensor, or a spin hall sensor. 8. The alignment system of claim 1 , further comprising a magnetic source located and configured to apply a magnetic field to at least a portion of a wafer carried on the substrate support. 9. The alignment system of claim 8 , wherein the magnetic source comprises an electro magnet. 10. The alignment system of claim 1 , wherein the sensor is configured to detect residual magnetic fields emitted by the alignment markers. 11. The alignment system of claim 1 , wherein the sensor is configured to detect magnetizations of the alignment markers. 12. A wafer comprising: a substrate comprising a semiconductor material; and one or more alignment markers comprising at least one of a ferromagnetic material or an antiferromagnetic material or any other material or structure detectable responsive to exposure to a proximate magnetic field. 13. The wafer of claim 12 , wherein the one or more alignment markers comprise a pattern of recesses formed in a surface of the wafer, the pattern of recesses being at least partially filled with at least one of the ferromagnetic material, the antiferromagnetic material, or any other material or structure detectable responsive to exposure to a proximate magnetic field. 14. The wafer of claim 12 , wherein the one or more alignment markers have longitudinal ends aligned along one of an X-axis, a Y-axis, or a Z-axis of a Cartesian space. 15. A wafer comprising: a substrate comprising a semiconductor material; and one or more alignment markers comprising one or more inductively powerable circuits within recesses of a pattern within the substrate. 16. An alignment system, comprising: a substrate support for supporting a wafer; a sensor movable over the wafer and configured to detect responses of alignment markers within the wafer; a magnetic source located and configured to apply a magnetic field to at least a portion of the wafer or drive a magnetization of the alignment markers within the wafer; and a controller operably coupled to the substrate support and sensor, the controller comprising: at least one processor; and at least one non-transitory computer-readable storage medium storing instructions thereon that, when executed by the at least one processor, cause the controller to: receive data related to detected responses of the alignment markers from the sensor; and responsive to the received data, determine locations of the alignment markers within the wafer. 17. The alignment system of claim 16 , wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to determine locations of the alignment markers within the wafer relative to an ideal grid based at least partially on the responses of the alignment markers. 18. The alignment system of claim 17 , wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to calculate a geometrical transformation model for aligning the wafer relative to the ideal grid. 19. The alignment system of claim 18 , wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to cause the alignment system to align the wafer responsive to the geometrical transformation model. 20. The alignment system of claim 16 , wherein the responses of the alignment markers comprise one or more of residual magnetic fields, magnetization, or photon emissions.

Assignees

Inventors

Classifications

  • for use before dicing · CPC title

  • for alignment · CPC title

  • H10P72/50Primary

    for positioning, orientation or alignment · CPC title

  • Marks applied to devices, e.g. for alignment or identification · CPC title

  • Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title

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What does patent US11520240B2 cover?
A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/50. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 06 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).