Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11515322-B2
Application number	US-202016890500-A
Country	US
Kind code	B2
Filing date	Jun 2, 2020
Priority date	Sep 26, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a peripheral circuit region including a first substrate and circuit elements on the first substrate; and
a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, a horizontal conductive layer between the second substrate and the gate electrodes, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, a cell region insulating layer covering a stacked structure of the gate electrode, and a second separation region extending vertically to penetrate through the second substrate from above,
wherein the second separation region includes a first region extending inwardly of the second substrate from above in trench form and a second region connected to a lower end of the first region within the second substrate, the second region having a width greater than a width of the first region and having a rounded external surface.

2. The semiconductor device as claimed in claim 1 , wherein the second separation region penetrates through the cell region insulating layer and the horizontal conductive layer from above, and extends to the second substrate.

3. The semiconductor device as claimed in claim 1 , wherein each of the first separation regions has a first width at an upper end of the first separation region, and the second separation region has a second width, greater than the first width, at an upper end of the second separation region.

4. The semiconductor device as claimed in claim 3 , wherein the second width ranges from about two times to about four times the first width.

5. The semiconductor device as claimed in claim 4 , wherein the second width ranges from about 300 nm to about 800 nm.

6. The semiconductor device as claimed in claim 1 , wherein the second separation region has a second width at an upper end of the first region, a third width less than the second width at a lower end of the first region, and a fourth width greater than the second width at a lower end of the second region.

7. The semiconductor device as claimed in claim 1 , wherein the second separation region has a lower surface substantially coplanar with a lower surface of the second substrate.

8. The semiconductor device as claimed in claim 1 , wherein the first separation regions have lower surfaces disposed at a level higher than a lower surface of the first region.

9. The semiconductor device as claimed in claim 1 , wherein the first separation regions and the second separation region are formed of an insulating material.

10. The semiconductor device as claimed in claim 1 , wherein:
the memory cell region includes a plurality of cell regions,
the second substrate includes a connection region extending between cell regions that are adjacent to each other in one direction, and
the second separation region penetrates through the connection region to divide the second substrate between the plurality of the cell regions.

11. The semiconductor device as claimed in claim 10 , wherein:
the gate electrodes are disposed within the plurality of cells regions such that the gate electrodes do not extend to the connection region, and
the second separation region does not penetrate through the gate electrodes.

12. The semiconductor device as claimed in claim 10 , wherein the memory cell region further includes source contact plugs disposed outside of the first separation regions in edge regions of the plurality of cell regions, the source contact plugs being electrically connected to the second substrate.

13. The semiconductor device as claimed in claim 1 , wherein the horizontal conductive layer includes first and second conductive layers that are vertically stacked.

14. The semiconductor device as claimed in claim 1 , wherein the channel structures include first and second channel structures vertically stacked on the second substrate.

15. The semiconductor device as claimed in claim 14 , wherein the first region of the second separation region includes two regions vertically stacked on the second substrate.

16. A semiconductor device, comprising:
a peripheral circuit region including a first substrate and circuit elements on the first substrate; and

a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width,
wherein the second separation region includes a first region extending from above in trench form, and a second region connected to a lower end of the first region, being in the second substrate, having a width greater than a width of the first region, and having a rounded external surface.

17. The semiconductor device as claimed in claim 16 , wherein the bent portion of the second separation region is disposed in the second substrate.

18. A semiconductor device, comprising:
a first substrate;
circuit elements on the first substrate;
a first insulating layer covering the circuit elements;
a second substrate disposed on the first insulating layer;
gate electrodes spaced apart from each other and vertically stacked on the second substrate;
a second insulating layer covering the gate electrodes; and
a separation region spaced apart from the gate electrodes, penetrating through the second insulating layer and the second substrate to vertically extend the second substrate, and having a bent portion,
wherein the separation region includes a first region extending from above in trench form, and a second region connected to a lower end of the first region.

19. The semiconductor device as claimed in claim 18 , wherein the second region connects to the first region within the second substrate, has a width greater than a width of the first region, and has a rounded external surface.

20. The semiconductor device as claimed in claim 19 , wherein the second region has a shape formed by isotropic etching.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Seogoo
• Jang Daehyun
• Sim Jaeryong
• Ahn Jongseon
• Han Jeehoon

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L27/11548

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11575 Primary

  Electricity · mapped topic

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title