Three-dimensional memory device containing hydrogen diffusion barrier layer for CMOS under array architecture and method of making thereof

Patent metadata

Field	Value
Publication number	US-10290645-B2
Application number	US-201715638672-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Jun 30, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
at least one semiconductor device;
a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer comprising a hydrogen diffusion barrier, and at least one second dielectric material layer overlying the at least one semiconductor device;
lower metal interconnect structures embedded within the dielectric layer stack, the lower metal interconnect structures comprising a lower metal line structure located below the silicon nitride layer;
a planar semiconductor material layer overlying the at least one second dielectric material layer;
a three-dimensional memory array overlying the dielectric layer stack and the planar semiconductor material layer, and including an alternating stack of insulating layers and electrically conductive layers, and including memory stack structures vertically extending through the alternating stack in a memory array region, wherein each of the memory stack structures includes a memory film and a vertical semiconductor channel that extend through the alternating stack, and the planar semiconductor material layer includes a horizontal semiconductor channel that is electrically connected to the vertical semiconductor channels of the memory stack structures;
a contact level dielectric layer overlying the three-dimensional memory array;
a through-stack contact via structure extending through the contact level dielectric layer, through the alternating stack, through an opening in the planar semiconductor material layer, through the at least one second dielectric material layer, and through the silicon nitride layer, and contacting the lower metal line structure; and
a through-stack insulating spacer laterally surrounding, and laterally enclosing, the through-stack contact via structure and extending through the contact level dielectric layer, through the alternating stack, through the opening in the planar semiconductor material layer, and through the at least one second dielectric material layer as a single continuous dielectric structure having a same dielectric composition throughout, but not extending through the silicon nitride layer.

2. The semiconductor structure of claim 1 , further comprising upper metal interconnect structures including an upper metal line structure, located over the three-dimensional memory array,
wherein:
the at least one semiconductor device comprises a CMOS driver circuit device located on a top surface of a substrate semiconductor layer of a substrate or on a top surface of the substrate;
the lower metal line structure contacts a bottom surface of the silicon nitride layer;
the through-stack contact via structure contacts a top surface of the lower metal line structure and a bottom surface of the upper metal line structure,
a set of conductive structures including the through-stack contact via structure and the lower metal line structure provides an electrically conductive path between the at least one semiconductor device and the upper metal line structure;
an inner sidewall of the through-stack insulating spacer contacts a sidewall of the through-stack contact via structure; and
an outer sidewall of the through-stack insulating spacer contacts sidewalls of each layer within the alternating stack.

3. The semiconductor structure of claim 1 , wherein the through-stack insulating spacer is laterally spaced from a sidewall of an opening of the planar semiconductor material layer by a portion of the at least one second dielectric material layer.

4. The semiconductor structure of claim 1 , wherein:
the through-stack insulating spacer directly contacts a top surface silicon nitride layer but does not extend through the entire thickness of the silicon nitride layer; and
the through-stack contact via structure is laterally spaced from the at least one second dielectric material layer by the through-stack insulating spacer.

5. The semiconductor structure of claim 1 , wherein:
the through-stack insulating spacer does not directly contact the silicon nitride layer; and
the through-stack contact via structure directly contacts the at least one second dielectric material layer.

6. The semiconductor structure of claim 1 , further comprising:
a terrace region including stepped surfaces of layers of the alternating stack;
a retro-stepped dielectric material portion overlying the stepped surfaces and located at levels of the alternating stack and above the at least one second dielectric material layer; and
a through-dielectric contact via structure vertically extending through the retro-stepped dielectric material portion, the at least one second dielectric material layer, and the silicon nitride layer and contacting a top surface of another lower metal line structure of the lower metal interconnect structures,
wherein the through-dielectric contact via structure directly contacts the retro-stepped dielectric material portion and the at least one second dielectric material layer.

7. The semiconductor structure of claim 1 , wherein:
the three-dimensional memory array comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the planar semiconductor material layer comprises a polysilicon layer;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the polysilicon layer;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the at least one semiconductor device comprises an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

8. The semiconductor structure of claim 1 , wherein the through-stack insulating spacer has an outer sidewall having a substantially cylindrical shape that extends between a top surface of the through-stack insulating spacer located at a top surface of the contact level dielectric layer and a bottom surface of the through-stack insulating spacer located within the at least one second dielectric material layer.

9. The semiconductor structure of claim 8 , wherein the through-stack insulating spacer does not have a uniform thickness around a vertical axis passing through a geometrical center thereof as a function of an azimuthal angle.

10. A semiconductor structure, comprising:
a semiconductor device;
a hydrogen diffusion barrier layer;
a lower metal line structure located below the hydrogen diffusion barrier layer;
a planar semiconductor material layer overlying the at least one second dielectric material layer;
an alternating stack of insulating layers and electrically conductive layers and overlying the planar semiconduct

Assignees

• Sandisk Technologies Llc

Inventors

• Nakatsuji Hiroshi
• Yoshizawa Kazutaka
• Ogawa Hiroyuki

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic