Polymer resin and compression mold chip scale package

Patent metadata

Field	Value
Publication number	US-11508679-B2
Application number	US-202017068172-A
Country	US
Kind code	B2
Filing date	Oct 12, 2020
Priority date	May 31, 2016
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

First claim

What is claimed is:

1. A chip scale package, comprising:
a semiconductor die having a top surface, a bottom surface, and side surfaces;
a metallization layer coupled on the top surface of the semiconductor die; and
a compression mold coupled on the bottom surface of the die, on the side surfaces of the die, and on a portion of the top surface of the die, the compression mold forming a strip along at least a part of a perimeter of the top surface where the strip directly contacts only the top surface.

2. The chip scale package of claim 1 , wherein the strip has an average width between 40 and 60 micrometers, inclusive.

3. The chip scale package of claim 1 , wherein the strip occupies between 20 percent and 40 percent, inclusive, of a total area of the top surface excluding metallization.

4. The chip scale package of claim 1 , wherein the compression mold is made of a material selected from the group consisting of: polyamides, polyimides, polyamide-imides, polyphenylene sulfide (PPS), polyether ether ketone (PEEK), and polyester fiberglass resin.

5. The chip scale package of claim 1 , wherein the top and bottom surfaces oppose each other.

6. A chip scale package, comprising:
a semiconductor die having a first largest planar surface, a second largest planar surface, and side surfaces across a thickness between the first largest planar surface and the second largest planar surface;
a metallization layer coupled on the first largest planar surface of the semiconductor die; and
a compression mold coupled on the second largest planar surface of the die, on the side surfaces of the die, and on a portion of the first largest planar surface of the die,
wherein a portion of the compression mold forms a strip along a perimeter of the first largest planar surface and is only in contact with the first largest planar surface.

7. The chip scale package of claim 6 , wherein the strip has a width between 40 and 60 micrometers.

8. The chip scale package of claim 6 , wherein the strip occupies between 20 percent and 40 percent of a total area of the first largest planar surface.

9. The chip scale package of claim 6 , wherein the compression mold is made of a material selected from the group consisting of: polyamides, polyimides, polyamide-imides, polyphenylene sulfide (PPS), polyether ether ketone (PEEK), and polyester fiberglass resin.

10. The chip scale package of claim 6 , wherein the first largest planar surface and second largest planar surface oppose each other.

11. A chip scale package, comprising:
a semiconductor die having a first largest planar surface, a second largest planar surface, and side surfaces across a thickness between the first largest planar surface and the second largest planar surface;
a metallization layer coupled on the first largest planar surface of the semiconductor die; and
a compression mold coupled on the second largest planar surface of the die, on the side surfaces of the die, and on a portion of the first largest planar surface of the die, the compression mold on the portion of the first largest planar surface contacting only the first largest planar surface.

12. The chip scale package of claim 11 , wherein the strip has a width between 40 and 60 micrometers.

13. The chip scale package of claim 11 , wherein the strip occupies between 20 percent and 40 percent of a total area of the first largest planar surface.

14. The chip scale package of claim 11 , wherein the compression mold is made of a material selected from the group consisting of: polyamides, polyimides, polyamide-imides, polyphenylene sulfide (PPS), polyether ether ketone (PEEK), and polyester fiberglass resin.

15. The chip scale package of claim 11 , wherein the first largest planar surface and second largest planar surface oppose each other.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Lin Yusheng
• Wang Soon Wei
• Chew Chee Hiong
• Carney Francis J

Classifications

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title