Chip package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9947716-B2
Application number	US-201615358852-A
Country	US
Kind code	B2
Filing date	Nov 22, 2016
Priority date	Nov 23, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

First claim

What is claimed is:

1. A manufacturing method of a chip package, comprising:
(a) grinding a carrier;
(b) patterning the carrier, such that the carrier has a recess, wherein the recess is defined by a bottom and a dam element of the carrier, and the dam element surrounds the bottom;
(c) using an adhesive layer to adhere the carrier to a first surface of a wafer, wherein the recess is present between the adhesive layer and the bottom of the carrier;
(d) grinding the bottom of the carrier, such that a thickness of the bottom is in a range from 10 μm to 250 μm;
(e) simultaneously impacting and attracting the bottom of the carrier, such that the bottom is separated from the dam element, and a wall surface of the dam element originally connected to the bottom forms a rough surface; and
(f) cutting the wafer and the dam element to form the chip package.

2. The manufacturing method of claim 1 , wherein step (e) comprises:
using a nozzle head connected to a pump to impact the bottom of the carrier; and
withdrawing gas by the pump, such that the nozzle head attracts the bottom that is separated from the dam element.

3. The manufacturing method of claim 1 , further comprising:
grinding a second surface of the wafer facing away from the first surface.

4. The manufacturing method of claim 3 , further comprising:
forming a through hole in the second surface of the wafer.

5. The manufacturing method of claim 4 , further comprising:
forming a patterned redistribution layer in the through hole and on the second surface of the wafer.

6. The manufacturing method of claim 5 , further comprising:
forming a passivation layer on the redistribution layer and the second surface of the wafer; and
patterning the passivation layer, such that the passivation layer has an opening to expose a portion of the redistribution layer.

7. The manufacturing method of claim 6 , further comprising:
forming a conductive structure on the redistribution layer that is in the opening of the passivation layer.

8. The manufacturing method of claim 7 , further comprising:
adhering the conductive structure to a protection tape.

9. The manufacturing method of claim 8 , further comprising:
adhering the dam element to a dicing tape; and
removing the protection tape.

10. The manufacturing method of claim 9 , wherein step (f) comprises:
cutting the wafer and the dam element on the dicing tape; and
extracting the chip package that is formed by cutting the wafer and the dam element from the dicing tape.

Assignees

• Xintec Inc

Inventors

• Ho Yen-Shih
• Yeh Hsiao-Lan
• Lin Chia-Sheng
• Chang Yi-Ming
• Lee Po-Han
• Wu Hui-Hsien
• Wu Jyun-Liang
• Chang Shu-Ming
• Huang Yu-Lung
• Lin Chien-Min

Classifications

• H10P72/0442

  Apparatus for placing on an insulating substrate, e.g. tape · CPC title

• H10P72/0402

  Apparatus for fluid treatment (H10P72/0441, H10P72/0448 take precedence) · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W76/42

  Fillings · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title