Semiconductor package in package

Patent metadata

Field	Value
Publication number	US-9466545-B1
Application number	US-67750607-A
Country	US
Kind code	B1
Filing date	Feb 21, 2007
Priority date	Feb 21, 2007
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate having at least one opening extending from a substrate top surface to a substrate bottom surface, wherein the substrate has a substrate conductive pattern disposed on the substrate top surface and a plurality of contacts disposed on the substrate bottom surface, the contacts being in electrical communication with the substrate conductive pattern;
at least two electronic components attached to the substrate top surface and electrically connected to the substrate conductive pattern;
an electronic module at least partially disposed within the opening and including a plurality of module contacts and a module body with a module top surface opposite to the module contacts, the electronic module further comprising:
a module substrate having a module conductive pattern disposed on a module substrate top surface, the plurality of module contacts disposed on a module substrate bottom surface, the module contacts being in electrical communication with the module conductive pattern; and
an electronic module component attached to the module substrate top surface and electrically connected to the module conductive pattern, wherein the module body covers the electronic module component, and wherein the module body entirely covers the module conductive pattern; and

a package body at least partially encapsulating the substrate, the electronic components and the electronic module such that the contacts of the substrate and the module contacts of the electronic module are exposed in a common exterior surface of the semiconductor package, the package body further overlapping and encapsulating the top surface of the module body, wherein the package body and the module body completely electrically isolate the module conductive pattern from the substrate conductive pattern.

2. The semiconductor package of claim 1 further in combination with a printed circuit board having a wiring pattern disposed thereon, the wiring pattern being configured to place the module contacts of the module into electrical communication with at least some of the contacts of the substrate when the contacts and the module contacts are each electrically connected to the wiring pattern.

3. The semiconductor package of claim 1 wherein the substrate includes:
a generally planar top surface having the conductive pattern disposed thereon;
a generally planar bottom surface having the contacts disposed thereon; and
a plurality of generally planar side surfaces extending between the top and bottom surfaces;
the side and bottom surfaces of the substrate being uncovered by the package body and thus exposed in the semiconductor package.

4. The semiconductor package of claim 1 wherein the electronic components comprise at least one active device and at least one passive device.

5. The semiconductor package of claim 4 wherein the active device is electrically connected to the substrate conductive pattern by conductive wires which are covered by the package body.

6. The semiconductor package of claim 1 wherein the electronic module component comprises at least one active device.

7. The semiconductor package of claim 6 wherein the active device is electrically connected to the module conductive pattern by conductive wires.

8. The semiconductor package of claim 1 wherein the module substrate includes:
a generally planar top surface having the module conductive pattern disposed thereon;
a generally planar bottom surface having the module contacts disposed thereon; and
a plurality of generally planar side surfaces extending between the top and bottom surfaces.

9. The semiconductor package of claim 8 wherein the module body covers the electronic module components and entirely covers the top surface of the module substrate, and wherein the package body covers the module body and the side surfaces of the module substrate with the bottom surfaces of the module substrate and the substrate being uncovered by the package body and thus exposed in the semiconductor package, and further extending in generally co-planar relation to each other.

10. The semiconductor package of claim 1 , wherein the module body defines multiple generally planar side surfaces each extending generally perpendicularly relative to the top surface of the module body in substantially flush, co-planar relation to respective ones of side surfaces of the module substrate.

11. The semiconductor package of claim 8 wherein the module further comprises a module body which covers the electronic module components and the top surface of the module substrate, the side surfaces of the module substrate, the bottom surface of the module substrate including the module conductive pattern thereon, and a portion of the module body each being covered by the package body, with a generally planar body surface defined by the module body and the bottom surface of the substrate being uncovered by the package body and extending in generally co-planar relation to each other.

12. The semiconductor package of claim 11 wherein the module conductive pattern is electrically connected to the substrate conductive pattern by conductive wires which are covered by the package body.

13. The semiconductor package of claim 1 , wherein the package body includes a pair of voids on opposing sides of the opening, the semiconductor package further comprising an RF shield overlapping the package body and extending into the pair of voids to electrically connect the RF shield to the conductive pattern of the substrate, the module laterally separated from at least one electronic component by the RF shield.

14. The semiconductor package of claim 1 , wherein:
the substrate includes two openings disposed therein;
a second electronic module is at least partially disposed within one of the openings; and
the second electronic module is electrically connected to the conductive pattern of the substrate.

15. The semiconductor package of claim 14 wherein the second electronic module is electrically connected to the conductive pattern of the substrate by conductive wires which are covered by the package body, and a portion of the second electronic module is exposed in the exterior surface of the semiconductor package having the contacts and the module contacts exposed therein.

16. A semiconductor package, comprising:
a substrate having at least one opening disposed therein, a substrate conductive pattern on a first major surface and a plurality of contacts disposed on a second major surface opposite to the first major surface, the substrate conductive pattern in electrical communication with the plurality of contacts;
at least two electronic components attached to the substrate and electrically connected to the contacts;
an internal semiconductor package at least partially disposed within the opening and including a plurality of contacts, the internal semiconductor package including an internal package body having side surfaces and a top surface opposite to the plurality of contacts, the internal semiconductor package further comprising:
an internal substrate having an internal substrate conductive pattern disposed on a top surface of the internal substrate, the plurality of contacts disposed on a bottom surface of the internal substrate, the plurality of contacts being in electrical communication with the internal substrate conductive pattern; and
an electronic component attached to the internal substrate and electrically connected to the internal substrate conductive pattern, wherein the internal package body covers the electronic component, and wherein each s

Assignees

• Scanlan Christopher M
• Berry Christopher J
• Amkor Technology Inc

Inventors

• Scanlan Christopher M
• Berry Christopher J

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title