Semiconductor packaging substrate, fabrication method and packaging process thereof

Patent metadata

Field	Value
Publication number	US-11508673-B2
Application number	US-202117202632-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Mar 19, 2020
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A semiconductor packaging substrate is provided and includes: an insulating layer, a thinned circuit structure formed of circuit layers and conductive posts stacked on one another embedding in the insulating layer, and a supporting structure formed on the insulating layer and having at least one through hole exposing the conductive posts. As such, before a subsequent packaging operation, the packaging substrate can be electrically tested and screened so as to prevent a defective packaging substrate from being misused in the subsequent packaging operation and hence avoid the loss of normal electronic elements. A method for fabricating a semiconductor packaging substrate and a packaging process using the semiconductor packaging substrate are also provided.

First claim

What is claimed is:

1. A semiconductor packaging substrate, comprising:
a circuit structure, comprising:
a plurality of circuit layers each having opposite first and second electrical surfaces;
a plurality of conductive posts each having opposite first and second end surfaces, wherein the plurality of conductive posts are vertically arranged on the first electrical surfaces of the circuit layers through the second end surfaces thereof; and
a plurality of insulating layers each having opposite first and second surfaces, wherein the plurality of insulating layers encapsulate the circuit layers and the conductive posts, and wherein the first end surfaces of the conductive posts on one side of the semiconductor packaging substrate are exposed from the first surface of the insulating layer and the second electrical surface of the circuit layer on another side of the semiconductor packaging substrate is exposed from the second surface of the insulating layer; and
a supporting structure arranged on the first surface of the insulating layer on one side of the circuit structure, wherein the supporting structure is used to increase an overall thickness of the semiconductor packaging substrate, wherein the supporting structure has at least one through hole for exposing the first end surfaces of the conductive posts to test an electrical state of the circuit layer and the conductive post, the supporting structure is made of a photosensitive insulating material, and the supporting structure is a removable and disposable structure.

2. The semiconductor packaging substrate of claim 1 , wherein the supporting structure is made of a photosensitive dielectric material or a photosensitive dry film material.

3. A semiconductor packaging process, comprising:
providing the semiconductor packaging substrate of claim 1 ;
inserting a contact terminal of a test equipment into the through hole to test an electrical state of the circuit layer and the conductive post;
after testing the electrical state of the circuit layer and the conductive post, bonding at least one electronic element onto the second surface of the insulating layer to electrically connect the electronic element and the circuit layer;
forming a packaging layer on the second surface of the insulating layer to encapsulate the electronic element; and
completely removing the supporting structure to expose the first surface of the insulating layer and the first end surfaces of the conductive posts.

4. The semiconductor packaging process of claim 3 , wherein the supporting structure is removed by a chemical method, laser, plasma, sandblasting or mechanical grinding.

5. The semiconductor packaging process of claim 3 , further comprising, after completely removing the supporting structure, forming a conductive element on the first surface of the insulating layer to electrically connect the first end surfaces of the conductive posts.

6. A method for fabricating a semiconductor packaging substrate, comprising:
providing a carrier;
forming a circuit layer and a conductive post on the carrier, wherein the circuit layer has opposite first and second electrical surfaces, and the conductive post has opposite first and second end surfaces, the circuit layer is attached onto the carrier through the second electrical surface thereof, and the conductive post is vertically arranged on the first electrical surface of the circuit layer through the second end surface thereof;
forming an insulating layer having opposite first and second surfaces on the carrier for encapsulating the circuit layer and the conductive post, wherein the first end surface of the conductive post is exposed from the first surface of the insulating layer and the second electrical surface of the circuit layer is exposed from the second surface of the insulating layer, such that the insulating layer, the circuit layer and the conductive post form a thinned circuit structure;
forming a supporting structure on the first surface of the insulating layer, wherein the supporting structure is used to increase an overall thickness of the semiconductor packaging substrate, wherein the supporting structure has at least one through hole for exposing the first end surface of the conductive post, the supporting structure is made of a photosensitive insulating material, and the supporting structure is a removable and disposable structure;
removing the carrier to expose the second surface of the insulating layer and the second electrical surface of the circuit layer, wherein the circuit structure and the supporting structure form a thinned packaging substrate; and
inserting a contact terminal of a test equipment into the through hole to test an electrical state of the circuit layer and the conductive post.

7. The method of claim 6 , wherein the through hole of the supporting structure is formed by lithography.

8. The method of claim 6 , wherein the supporting structure is made of a photosensitive dielectric material or a photosensitive dry film material.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Chou Pao-Hung
• Yu Chun-Hsien

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title