Adaptive cache partitioning

Patent metadata

Field	Value
Publication number	US-11507516-B2
Application number	US-202016997811-A
Country	US
Kind code	B2
Filing date	Aug 19, 2020
Priority date	Aug 19, 2020
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

Described apparatuses and methods partition a cache memory based, at least in part, on a metric indicative of prefetch performance. The amount of cache memory allocated for metadata related to prefetch operations versus cache storage can be adjusted based on operating conditions. Thus, the cache memory can be partitioned into a first portion allocated for metadata pertaining to an address space (prefetch metadata) and a second portion allocated for data associated with the address space (cache data). The amount of cache memory allocated to the first portion can be increased under workloads that are suitable for prefetching and decreased otherwise. The first portion may include one or more cache units, cache lines, cache ways, cache sets, or other resources of the cache memory.

First claim

The invention claimed is:

1. A method, comprising:
allocating a first portion of a cache memory for metadata pertaining to an address space;
writing data associated with addresses of the address space to a second portion of the cache memory different from the first portion of the cache memory; and
modifying a size of the first portion of the cache memory allocated for the metadata pertaining to the address space based, at least in part, on a metric pertaining to data prefetched into the second portion of the cache memory.

2. The method of claim 1 , further comprising:
updating the metadata maintained within the first portion of the cache memory in response to requests pertaining to addresses of the address space; and
prefetching data into the second portion of the cache memory based, at least in part, on the metadata pertaining to the address space maintained within the first portion of the cache memory.

3. The method of claim 1 , further comprising maintaining within the first portion of the cache memory one or more of an address sequence, address history, index table, delta sequence, stride pattern, correlation pattern, feature vector, machine-learned (ML) feature, ML feature vector, ML model, or ML modeling data.

4. The method of claim 1 , further comprising:
monitoring the metric pertaining to the data prefetched into the second portion of the cache memory; and
modifying the size of the first portion of the cache memory in response to the monitoring.

5. The method of claim 4 , further comprising monitoring one or more of a prefetch hit rate, quantity of useful prefetches, quantity of bad prefetches, or ratio of useful prefetches to bad prefetches.

6. The method of claim 1 , further comprising one of:
increasing the size of the first portion of the cache memory allocated for the metadata pertaining to the address space in response to the metric exceeding a first threshold; or
decreasing the size of the first portion of the cache memory allocated for the metadata pertaining to the address space in response to the metric being below a second threshold.

7. The method of claim 6 , further comprising one of:
decreasing a size of the second portion of the cache memory in response to the metric exceeding the first threshold; or
increasing the size of the second portion of the cache memory in response to the metric being below the second threshold.

8. The method of claim 1 , further comprising increasing the size of the first portion of the cache memory allocated for the metadata pertaining to the address space in response to the size of the first portion of the cache memory being below a metadata capacity threshold and one or more of:
a prefetch performance metric that is above a prefetch performance threshold; or
a cache performance metric that is below a cache performance threshold.

9. The method of claim 1 , further comprising decreasing the size of the first portion of the cache memory allocated for the metadata pertaining to the address space in response to the size of the first portion of the cache memory being above a prefetch capacity threshold and one or more of:
a prefetch performance metric that is below a prefetch performance threshold; or
a cache performance metric that is above a cache performance threshold.

10. The method of claim 1 , further comprising:
responsive to allocating a group of cache units of the cache memory for the metadata pertaining to the address space,
removing the group of cache units from an address mapping scheme, and
adding the group of cache units to a metadata mapping scheme.

11. The method of claim 1 , further comprising:
responsive to allocating a group of cache units from the second portion to the first portion,
evicting cache data from cache units of the group of cache units, and
disabling cache tags associated with the cache units of the group of cache units.

12. The method of claim 11 , further comprising:
evicting cache data from a selected cache unit, the selected cache unit to remain allocated to the second portion; and
moving cache data stored within a cache unit of the group of cache units being allocated from the second portion to the first portion to the selected cache unit.

13. The method of claim 1 , further comprising reducing an amount of cache memory allocated for the metadata pertaining to the address space from a first group of cache units of the cache memory to a second group of cache units of the cache memory, the second group smaller than the first group, comprising:
compacting the metadata for storage within the second group of cache units;
moving metadata stored within a cache unit included in the first group of cache units to a cache unit included in the second group of cache units; and
allocating one or more cache units included in the first group of cache units to the second portion of the cache memory.

14. The method of claim 1 , further comprising:
allocating a quantity of ways of the cache memory for the metadata pertaining to the address space; and
modifying the quantity of ways of the cache memory allocated for the metadata pertaining to the address space based, at least in part, on the metric.

15. The method of claim 14 , further comprising:
dividing the ways of a set of the cache memory into a first group allocated for the metadata pertaining to the address space and a second group allocated for caching data associated with the address space; and
moving cache data from a way within the first group to a way within the second group.

16. The method of claim 1 , further comprising:
allocating a quantity of sets of the cache memory for the metadata pertaining to the address space; and
modifying the quantity of sets of the cache memory allocated for the metadata pertaining to the address space based, at least in part, on the metric.

17. The method of claim 1 , further comprising:
selecting a subset of the metadata pertaining to the address space in response to decreasing a capacity of the first portion of the cache memory from a first capacity to a second capacity smaller than the first capacity; and
storing the selected subset of the metadata pertaining to the address space within the decreased capacity of the first portion of the cache memory.

18. An apparatus, comprising:
a memory array configured as a cache memory; and
logic coupled to the memory array, the logic configured to:
allocate a first portion of the cache memory to store metadata pertaining to an address space,
determine a metric pertaining to cache data loaded into a second portion of the cache memory, the second portion different from the first portion, and
modify an amount of the cache memory allocated to the first portion based, at least in part, on the determined metric.

19. The apparatus of claim 18 , further comprising partition logic configured to allocate a first group of cache units of a plurality of cache units of the cache memory to the first portion and a second, different group of cache units of the plurality of cache units to the second portion.

20. The apparatus of claim 19 , wherein the cache units of the cache memory comprise one or more of memory units, blocks, memory blocks, cache blocks, cache memory blocks, pages, memory pages, cache pages, cache memory pages, cache lines, hardware cache lines, ways, rows of a memory array, or columns of a memory array.

21. The apparatus of claim 19 , further comprising prefetch logic configured to:
store metadata pertaining to the address space

Assignees

• Micron Technology Inc

Inventors

• Roberts David Andrew
• Pawlowski Joseph Thomas

Classifications

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F2212/282

  Partitioned cache · CPC title

• G06F2212/6026

  Prefetching based on access pattern detection, e.g. stride based prefetch · CPC title

• G06F12/0862

  with prefetch · CPC title